Commit ed4cbc81 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle

MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}

activate_mm() and switch_mm() call get_new_mmu_context() which in turn
can enable the HTW before the entryhi is changed with the new ASID.
Since the latter will enable the HTW in local_flush_tlb_all(),
then there is a small timing window where the HTW is running with the
new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD
hasn't assigned a new one yet. In order to prevent that, we introduce a
simple htw counter to avoid starting HTW accidentally due to nested
htw_{start,stop}() sequences. Moreover, since various IPI calls can
enforce TLB flushing operations on a different core, such an operation
may interrupt another htw_{stop,start} in progress leading inconsistent
updates of the htw_seq variable. In order to avoid that, we disable the
interrupts whenever we update that variable.
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9118/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent fde3538a
...@@ -84,6 +84,11 @@ struct cpuinfo_mips { ...@@ -84,6 +84,11 @@ struct cpuinfo_mips {
* (shifted by _CACHE_SHIFT) * (shifted by _CACHE_SHIFT)
*/ */
unsigned int writecombine; unsigned int writecombine;
/*
* Simple counter to prevent enabling HTW in nested
* htw_start/htw_stop calls
*/
unsigned int htw_seq;
} __attribute__((aligned(SMP_CACHE_BYTES))); } __attribute__((aligned(SMP_CACHE_BYTES)));
extern struct cpuinfo_mips cpu_data[]; extern struct cpuinfo_mips cpu_data[];
......
...@@ -25,7 +25,6 @@ do { \ ...@@ -25,7 +25,6 @@ do { \
if (cpu_has_htw) { \ if (cpu_has_htw) { \
write_c0_pwbase(pgd); \ write_c0_pwbase(pgd); \
back_to_back_c0_hazard(); \ back_to_back_c0_hazard(); \
htw_reset(); \
} \ } \
} while (0) } while (0)
...@@ -144,6 +143,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, ...@@ -144,6 +143,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
unsigned long flags; unsigned long flags;
local_irq_save(flags); local_irq_save(flags);
htw_stop();
/* Check if our ASID is of an older version and thus invalid */ /* Check if our ASID is of an older version and thus invalid */
if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
get_new_mmu_context(next, cpu); get_new_mmu_context(next, cpu);
...@@ -156,6 +156,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, ...@@ -156,6 +156,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
*/ */
cpumask_clear_cpu(cpu, mm_cpumask(prev)); cpumask_clear_cpu(cpu, mm_cpumask(prev));
cpumask_set_cpu(cpu, mm_cpumask(next)); cpumask_set_cpu(cpu, mm_cpumask(next));
htw_start();
local_irq_restore(flags); local_irq_restore(flags);
} }
...@@ -182,6 +183,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) ...@@ -182,6 +183,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
local_irq_save(flags); local_irq_save(flags);
htw_stop();
/* Unconditionally get a new ASID. */ /* Unconditionally get a new ASID. */
get_new_mmu_context(next, cpu); get_new_mmu_context(next, cpu);
...@@ -191,6 +193,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) ...@@ -191,6 +193,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
/* mark mmu ownership change */ /* mark mmu ownership change */
cpumask_clear_cpu(cpu, mm_cpumask(prev)); cpumask_clear_cpu(cpu, mm_cpumask(prev));
cpumask_set_cpu(cpu, mm_cpumask(next)); cpumask_set_cpu(cpu, mm_cpumask(next));
htw_start();
local_irq_restore(flags); local_irq_restore(flags);
} }
...@@ -205,6 +208,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu) ...@@ -205,6 +208,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
unsigned long flags; unsigned long flags;
local_irq_save(flags); local_irq_save(flags);
htw_stop();
if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
get_new_mmu_context(mm, cpu); get_new_mmu_context(mm, cpu);
...@@ -213,6 +217,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu) ...@@ -213,6 +217,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
/* will get a new context next time */ /* will get a new context next time */
cpu_context(cpu, mm) = 0; cpu_context(cpu, mm) = 0;
} }
htw_start();
local_irq_restore(flags); local_irq_restore(flags);
} }
......
...@@ -99,19 +99,31 @@ extern void paging_init(void); ...@@ -99,19 +99,31 @@ extern void paging_init(void);
#define htw_stop() \ #define htw_stop() \
do { \ do { \
unsigned long flags; \
\
if (cpu_has_htw) { \ if (cpu_has_htw) { \
write_c0_pwctl(read_c0_pwctl() & \ local_irq_save(flags); \
~(1 << MIPS_PWCTL_PWEN_SHIFT)); \ if(!raw_current_cpu_data.htw_seq++) { \
back_to_back_c0_hazard(); \ write_c0_pwctl(read_c0_pwctl() & \
~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
back_to_back_c0_hazard(); \
} \
local_irq_restore(flags); \
} \ } \
} while(0) } while(0)
#define htw_start() \ #define htw_start() \
do { \ do { \
unsigned long flags; \
\
if (cpu_has_htw) { \ if (cpu_has_htw) { \
write_c0_pwctl(read_c0_pwctl() | \ local_irq_save(flags); \
(1 << MIPS_PWCTL_PWEN_SHIFT)); \ if (!--raw_current_cpu_data.htw_seq) { \
back_to_back_c0_hazard(); \ write_c0_pwctl(read_c0_pwctl() | \
(1 << MIPS_PWCTL_PWEN_SHIFT)); \
back_to_back_c0_hazard(); \
} \
local_irq_restore(flags); \
} \ } \
} while(0) } while(0)
......
...@@ -424,8 +424,10 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) ...@@ -424,8 +424,10 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
if (config3 & MIPS_CONF3_MSA) if (config3 & MIPS_CONF3_MSA)
c->ases |= MIPS_ASE_MSA; c->ases |= MIPS_ASE_MSA;
/* Only tested on 32-bit cores */ /* Only tested on 32-bit cores */
if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
c->htw_seq = 0;
c->options |= MIPS_CPU_HTW; c->options |= MIPS_CPU_HTW;
}
return config3 & MIPS_CONF_M; return config3 & MIPS_CONF_M;
} }
......
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