Commit ed93b714 authored by Jacob Pan's avatar Jacob Pan Committed by Rafael J. Wysocki

powercap / RAPL: add support for ValleyView Soc

This patch adds support for RAPL on Intel ValleyView based SoC
platforms, such as Baytrail.

Besides adding CPU ID, special energy unit encoding is handled
for ValleyView.
Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 319e2e3f
...@@ -833,6 +833,11 @@ static int rapl_write_data_raw(struct rapl_domain *rd, ...@@ -833,6 +833,11 @@ static int rapl_write_data_raw(struct rapl_domain *rd,
return 0; return 0;
} }
static const struct x86_cpu_id energy_unit_quirk_ids[] = {
{ X86_VENDOR_INTEL, 6, 0x37},/* VLV */
{}
};
static int rapl_check_unit(struct rapl_package *rp, int cpu) static int rapl_check_unit(struct rapl_package *rp, int cpu)
{ {
u64 msr_val; u64 msr_val;
...@@ -853,8 +858,11 @@ static int rapl_check_unit(struct rapl_package *rp, int cpu) ...@@ -853,8 +858,11 @@ static int rapl_check_unit(struct rapl_package *rp, int cpu)
* time unit: 1/time_unit_divisor Seconds * time unit: 1/time_unit_divisor Seconds
*/ */
value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
rp->energy_unit_divisor = 1 << value; /* some CPUs have different way to calculate energy unit */
if (x86_match_cpu(energy_unit_quirk_ids))
rp->energy_unit_divisor = 1000000 / (1 << value);
else
rp->energy_unit_divisor = 1 << value;
value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
rp->power_unit_divisor = 1 << value; rp->power_unit_divisor = 1 << value;
...@@ -941,6 +949,7 @@ static void package_power_limit_irq_restore(int package_id) ...@@ -941,6 +949,7 @@ static void package_power_limit_irq_restore(int package_id)
static const struct x86_cpu_id rapl_ids[] = { static const struct x86_cpu_id rapl_ids[] = {
{ X86_VENDOR_INTEL, 6, 0x2a},/* SNB */ { X86_VENDOR_INTEL, 6, 0x2a},/* SNB */
{ X86_VENDOR_INTEL, 6, 0x2d},/* SNB EP */ { X86_VENDOR_INTEL, 6, 0x2d},/* SNB EP */
{ X86_VENDOR_INTEL, 6, 0x37},/* VLV */
{ X86_VENDOR_INTEL, 6, 0x3a},/* IVB */ { X86_VENDOR_INTEL, 6, 0x3a},/* IVB */
{ X86_VENDOR_INTEL, 6, 0x45},/* HSW */ { X86_VENDOR_INTEL, 6, 0x45},/* HSW */
/* TODO: Add more CPU IDs after testing */ /* TODO: Add more CPU IDs after testing */
......
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