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nexedi
linux
Commits
ee059485
Commit
ee059485
authored
Jan 28, 2013
by
Stephen Warren
Browse files
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Plain Diff
Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114
Conflicts: arch/arm/mach-tegra/platsmp.c
parents
1d328606
80d93756
Changes
12
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12 changed files
with
141 additions
and
68 deletions
+141
-68
arch/arm/boot/dts/tegra20.dtsi
arch/arm/boot/dts/tegra20.dtsi
+17
-0
arch/arm/boot/dts/tegra30.dtsi
arch/arm/boot/dts/tegra30.dtsi
+29
-0
arch/arm/include/asm/cputype.h
arch/arm/include/asm/cputype.h
+33
-0
arch/arm/include/asm/smp_scu.h
arch/arm/include/asm/smp_scu.h
+17
-0
arch/arm/kernel/perf_event.c
arch/arm/kernel/perf_event.c
+3
-13
arch/arm/kernel/perf_event_cpu.c
arch/arm/kernel/perf_event_cpu.c
+27
-24
arch/arm/kernel/perf_event_v6.c
arch/arm/kernel/perf_event_v6.c
+2
-2
arch/arm/kernel/perf_event_v7.c
arch/arm/kernel/perf_event_v7.c
+9
-9
arch/arm/kernel/perf_event_xscale.c
arch/arm/kernel/perf_event_xscale.c
+1
-1
arch/arm/mach-omap2/omap-smp.c
arch/arm/mach-omap2/omap-smp.c
+1
-1
arch/arm/mach-omap2/omap44xx.h
arch/arm/mach-omap2/omap44xx.h
+0
-1
arch/arm/mach-tegra/platsmp.c
arch/arm/mach-tegra/platsmp.c
+2
-17
No files found.
arch/arm/boot/dts/tegra20.dtsi
View file @
ee059485
...
...
@@ -489,6 +489,23 @@ sdhci@c8000600 {
status = "disabled";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 56 0x04
...
...
arch/arm/boot/dts/tegra30.dtsi
View file @
ee059485
...
...
@@ -506,6 +506,35 @@ sdhci@78000600 {
status = "disabled";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 144 0x04
...
...
arch/arm/include/asm/cputype.h
View file @
ee059485
...
...
@@ -64,6 +64,24 @@ extern unsigned int processor_id;
#define read_cpuid_ext(reg) 0
#endif
#define ARM_CPU_IMP_ARM 0x41
#define ARM_CPU_IMP_INTEL 0x69
#define ARM_CPU_PART_ARM1136 0xB360
#define ARM_CPU_PART_ARM1156 0xB560
#define ARM_CPU_PART_ARM1176 0xB760
#define ARM_CPU_PART_ARM11MPCORE 0xB020
#define ARM_CPU_PART_CORTEX_A8 0xC080
#define ARM_CPU_PART_CORTEX_A9 0xC090
#define ARM_CPU_PART_CORTEX_A5 0xC050
#define ARM_CPU_PART_CORTEX_A15 0xC0F0
#define ARM_CPU_PART_CORTEX_A7 0xC070
#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
#define ARM_CPU_XSCALE_ARCH_V1 0x2000
#define ARM_CPU_XSCALE_ARCH_V2 0x4000
#define ARM_CPU_XSCALE_ARCH_V3 0x6000
/*
* The CPU ID never changes at run time, so we might as well tell the
* compiler that it's constant. Use this function to read the CPU ID
...
...
@@ -74,6 +92,21 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
return
read_cpuid
(
CPUID_ID
);
}
static
inline
unsigned
int
__attribute_const__
read_cpuid_implementor
(
void
)
{
return
(
read_cpuid_id
()
&
0xFF000000
)
>>
24
;
}
static
inline
unsigned
int
__attribute_const__
read_cpuid_part_number
(
void
)
{
return
read_cpuid_id
()
&
0xFFF0
;
}
static
inline
unsigned
int
__attribute_const__
xscale_cpu_arch_version
(
void
)
{
return
read_cpuid_part_number
()
&
ARM_CPU_XSCALE_ARCH_MASK
;
}
static
inline
unsigned
int
__attribute_const__
read_cpuid_cachetype
(
void
)
{
return
read_cpuid
(
CPUID_CACHETYPE
);
...
...
arch/arm/include/asm/smp_scu.h
View file @
ee059485
...
...
@@ -6,6 +6,23 @@
#define SCU_PM_POWEROFF 3
#ifndef __ASSEMBLER__
#include <asm/cputype.h>
static
inline
bool
scu_a9_has_base
(
void
)
{
return
read_cpuid_part_number
()
==
ARM_CPU_PART_CORTEX_A9
;
}
static
inline
unsigned
long
scu_a9_get_base
(
void
)
{
unsigned
long
pa
;
asm
(
"mrc p15, 4, %0, c15, c0, 0"
:
"=r"
(
pa
));
return
pa
;
}
unsigned
int
scu_get_core_count
(
void
__iomem
*
);
void
scu_enable
(
void
__iomem
*
);
int
scu_power_mode
(
void
__iomem
*
,
unsigned
int
);
...
...
arch/arm/kernel/perf_event.c
View file @
ee059485
...
...
@@ -149,12 +149,6 @@ u64 armpmu_event_update(struct perf_event *event)
static
void
armpmu_read
(
struct
perf_event
*
event
)
{
struct
hw_perf_event
*
hwc
=
&
event
->
hw
;
/* Don't read disabled counters! */
if
(
hwc
->
idx
<
0
)
return
;
armpmu_event_update
(
event
);
}
...
...
@@ -207,8 +201,6 @@ armpmu_del(struct perf_event *event, int flags)
struct
hw_perf_event
*
hwc
=
&
event
->
hw
;
int
idx
=
hwc
->
idx
;
WARN_ON
(
idx
<
0
);
armpmu_stop
(
event
,
PERF_EF_UPDATE
);
hw_events
->
events
[
idx
]
=
NULL
;
clear_bit
(
idx
,
hw_events
->
used_mask
);
...
...
@@ -358,7 +350,7 @@ __hw_perf_event_init(struct perf_event *event)
{
struct
arm_pmu
*
armpmu
=
to_arm_pmu
(
event
->
pmu
);
struct
hw_perf_event
*
hwc
=
&
event
->
hw
;
int
mapping
,
err
;
int
mapping
;
mapping
=
armpmu
->
map_event
(
event
);
...
...
@@ -407,14 +399,12 @@ __hw_perf_event_init(struct perf_event *event)
local64_set
(
&
hwc
->
period_left
,
hwc
->
sample_period
);
}
err
=
0
;
if
(
event
->
group_leader
!=
event
)
{
err
=
validate_group
(
event
);
if
(
err
)
if
(
validate_group
(
event
)
!=
0
);
return
-
EINVAL
;
}
return
err
;
return
0
;
}
static
int
armpmu_event_init
(
struct
perf_event
*
event
)
...
...
arch/arm/kernel/perf_event_cpu.c
View file @
ee059485
...
...
@@ -147,7 +147,7 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
cpu_pmu
->
free_irq
=
cpu_pmu_free_irq
;
/* Ensure the PMU has sane values out of reset. */
if
(
cpu_pmu
&&
cpu_pmu
->
reset
)
if
(
cpu_pmu
->
reset
)
on_each_cpu
(
cpu_pmu
->
reset
,
cpu_pmu
,
1
);
}
...
...
@@ -201,48 +201,46 @@ static struct platform_device_id cpu_pmu_plat_device_ids[] = {
static
int
probe_current_pmu
(
struct
arm_pmu
*
pmu
)
{
int
cpu
=
get_cpu
();
unsigned
long
cpuid
=
read_cpuid_id
();
unsigned
long
implementor
=
(
cpuid
&
0xFF000000
)
>>
24
;
unsigned
long
part_number
=
(
cpuid
&
0xFFF0
);
unsigned
long
implementor
=
read_cpuid_implementor
();
unsigned
long
part_number
=
read_cpuid_part_number
();
int
ret
=
-
ENODEV
;
pr_info
(
"probing PMU on CPU %d
\n
"
,
cpu
);
/* ARM Ltd CPUs. */
if
(
0x41
==
implementor
)
{
if
(
implementor
==
ARM_CPU_IMP_ARM
)
{
switch
(
part_number
)
{
case
0xB360
:
/* ARM1136 */
case
0xB560
:
/* ARM1156 */
case
0xB760
:
/* ARM1176 */
case
ARM_CPU_PART_ARM1136
:
case
ARM_CPU_PART_ARM1156
:
case
ARM_CPU_PART_ARM1176
:
ret
=
armv6pmu_init
(
pmu
);
break
;
case
0xB020
:
/* ARM11mpcore */
case
ARM_CPU_PART_ARM11MPCORE
:
ret
=
armv6mpcore_pmu_init
(
pmu
);
break
;
case
0xC080
:
/* Cortex-A8 */
case
ARM_CPU_PART_CORTEX_A8
:
ret
=
armv7_a8_pmu_init
(
pmu
);
break
;
case
0xC090
:
/* Cortex-A9 */
case
ARM_CPU_PART_CORTEX_A9
:
ret
=
armv7_a9_pmu_init
(
pmu
);
break
;
case
0xC050
:
/* Cortex-A5 */
case
ARM_CPU_PART_CORTEX_A5
:
ret
=
armv7_a5_pmu_init
(
pmu
);
break
;
case
0xC0F0
:
/* Cortex-A15 */
case
ARM_CPU_PART_CORTEX_A15
:
ret
=
armv7_a15_pmu_init
(
pmu
);
break
;
case
0xC070
:
/* Cortex-A7 */
case
ARM_CPU_PART_CORTEX_A7
:
ret
=
armv7_a7_pmu_init
(
pmu
);
break
;
}
/* Intel CPUs [xscale]. */
}
else
if
(
0x69
==
implementor
)
{
part_number
=
(
cpuid
>>
13
)
&
0x7
;
switch
(
part_number
)
{
case
1
:
}
else
if
(
implementor
==
ARM_CPU_IMP_INTEL
)
{
switch
(
xscale_cpu_arch_version
())
{
case
ARM_CPU_XSCALE_ARCH_V1
:
ret
=
xscale1pmu_init
(
pmu
);
break
;
case
2
:
case
ARM_CPU_XSCALE_ARCH_V
2
:
ret
=
xscale2pmu_init
(
pmu
);
break
;
}
...
...
@@ -279,17 +277,22 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
}
if
(
ret
)
{
pr_info
(
"failed to register PMU devices!"
);
kfree
(
pmu
);
return
ret
;
pr_info
(
"failed to probe PMU!"
);
goto
out_free
;
}
cpu_pmu
=
pmu
;
cpu_pmu
->
plat_device
=
pdev
;
cpu_pmu_init
(
cpu_pmu
);
armpmu_register
(
cpu_pmu
,
PERF_TYPE_RAW
);
ret
=
armpmu_register
(
cpu_pmu
,
PERF_TYPE_RAW
);
return
0
;
if
(
!
ret
)
return
0
;
out_free:
pr_info
(
"failed to register PMU devices!"
);
kfree
(
pmu
);
return
ret
;
}
static
struct
platform_driver
cpu_pmu_driver
=
{
...
...
arch/arm/kernel/perf_event_v6.c
View file @
ee059485
...
...
@@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_ICACHE_MISS
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
...
...
@@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_ICACHE_MISS
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
...
...
arch/arm/kernel/perf_event_v7.c
View file @
ee059485
...
...
@@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
...
...
@@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
...
...
@@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
/*
* The prefetch counters don't differentiate between the I
...
...
@@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
...
...
@@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
...
...
arch/arm/kernel/perf_event_xscale.c
View file @
ee059485
...
...
@@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_ICACHE_MISS
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
...
...
arch/arm/mach-omap2/omap-smp.c
View file @
ee059485
...
...
@@ -215,7 +215,7 @@ static void __init omap4_smp_init_cpus(void)
* Currently we can't call ioremap here because
* SoC detection won't work until after init_early.
*/
scu_base
=
OMAP2_L4_IO_ADDRESS
(
OMAP44XX_SCU_BASE
);
scu_base
=
OMAP2_L4_IO_ADDRESS
(
scu_a9_get_base
()
);
BUG_ON
(
!
scu_base
);
ncores
=
scu_get_core_count
(
scu_base
);
}
else
if
(
cpu_id
==
CPU_CORTEX_A15
)
{
...
...
arch/arm/mach-omap2/omap44xx.h
View file @
ee059485
...
...
@@ -40,7 +40,6 @@
#define OMAP44XX_GIC_DIST_BASE 0x48241000
#define OMAP44XX_GIC_CPU_BASE 0x48240100
#define OMAP44XX_IRQ_GIC_START 32
#define OMAP44XX_SCU_BASE 0x48240000
#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
#define OMAP44XX_L2CACHE_BASE 0x48242000
#define OMAP44XX_WKUPGEN_BASE 0x48281000
...
...
arch/arm/mach-tegra/platsmp.c
View file @
ee059485
...
...
@@ -38,7 +38,6 @@
extern
void
tegra_secondary_startup
(
void
);
static
cpumask_t
tegra_cpu_init_mask
;
static
void
__iomem
*
scu_base
=
IO_ADDRESS
(
TEGRA_ARM_PERIF_BASE
);
#define EVP_CPU_RESET_VECTOR \
(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
...
...
@@ -177,23 +176,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *
return
status
;
}
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
static
void
__init
tegra_smp_init_cpus
(
void
)
{
unsigned
int
i
,
ncores
=
scu_get_core_count
(
scu_base
);
if
(
ncores
>
nr_cpu_ids
)
{
pr_warn
(
"SMP: %u cores greater than maximum (%u), clipping
\n
"
,
ncores
,
nr_cpu_ids
);
ncores
=
nr_cpu_ids
;
}
for
(
i
=
0
;
i
<
ncores
;
i
++
)
set_cpu_possible
(
i
,
true
);
set_smp_cross_call
(
gic_raise_softirq
);
}
...
...
@@ -202,7 +186,8 @@ static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
/* Always mark the boot CPU (CPU0) as initialized. */
cpumask_set_cpu
(
0
,
&
tegra_cpu_init_mask
);
scu_enable
(
scu_base
);
if
(
scu_a9_has_base
())
scu_enable
(
IO_ADDRESS
(
scu_a9_get_base
()));
}
struct
smp_operations
tegra_smp_ops
__initdata
=
{
...
...
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