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Commit ee1ae4d7 authored by Sascha Hauer's avatar Sascha Hauer
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ARM i.MX51: Full iomux support 

This iomux file has been constructed from the Freescale pinmux tool.
It contains all pins from the tool, but the datasheet lists some
configurations not present in the tool, these are not yet added.
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent 96f3e256
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Showing with 1604 additions and 431 deletions
arch/arm/mach-mx5/board-cpuimx51.c
View file @ ee1ae4d7
......@@ -121,15 +121,15 @@ static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
MX51_PAD_UART1_CTS__UART1_CTS,
/* I2C2 */
MX51_PAD_GPIO_1_2__I2C2_SCL,
MX51_PAD_GPIO_1_3__I2C2_SDA,
MX51_PAD_NANDF_D10__GPIO_3_30,
MX51_PAD_GPIO1_2__I2C2_SCL,
MX51_PAD_GPIO1_3__I2C2_SDA,
MX51_PAD_NANDF_D10__GPIO3_30,
/* QUART IRQ */
MX51_PAD_NANDF_D15__GPIO_3_25,
MX51_PAD_NANDF_D14__GPIO_3_26,
MX51_PAD_NANDF_D13__GPIO_3_27,
MX51_PAD_NANDF_D12__GPIO_3_28,
MX51_PAD_NANDF_D15__GPIO3_25,
MX51_PAD_NANDF_D14__GPIO3_26,
MX51_PAD_NANDF_D13__GPIO3_27,
MX51_PAD_NANDF_D12__GPIO3_28,
/* USB HOST1 */
MX51_PAD_USBH1_CLK__USBH1_CLK,
......
arch/arm/mach-mx5/board-cpuimx51sd.c
View file @ ee1ae4d7
......@@ -65,9 +65,6 @@
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
#define MX51_USB_PLL_DIV_24_MHZ 0x02
#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \
MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
......@@ -88,30 +85,33 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
MX51_PAD_USBH1_DATA6__USBH1_DATA6,
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
MX51_PAD_USBH1_STP__USBH1_STP,
MX51_PAD_EIM_CS3__GPIO_2_28, /* PHY nRESET */
MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
/* FEC */
MX51_PAD_EIM_DTACK__GPIO_2_31, /* PHY nRESET */
MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
/* HSI2C */
MX51_PAD_I2C1_CLK__GPIO_4_16,
MX51_PAD_I2C1_DAT__GPIO_4_17,
MX51_PAD_I2C1_CLK__GPIO4_16,
MX51_PAD_I2C1_DAT__GPIO4_17,
/* CAN */
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
MX51_PAD_CSPI1_SS0__GPIO_4_24, /* nCS */
MX51_PAD_CSI2_PIXCLK__GPIO_4_15, /* nReset */
MX51_PAD_GPIO_1_1__GPIO_1_1, /* IRQ */
MX51_PAD_GPIO_1_4__GPIO_1_4, /* Control signals */
MX51_PAD_GPIO_1_6__GPIO_1_6,
MX51_PAD_GPIO_1_7__GPIO_1_7,
MX51_PAD_GPIO_1_8__GPIO_1_8,
MX51_PAD_GPIO_1_9__GPIO_1_9,
MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
MX51_PAD_GPIO1_6__GPIO1_6,
MX51_PAD_GPIO1_7__GPIO1_7,
MX51_PAD_GPIO1_8__GPIO1_8,
MX51_PAD_GPIO1_9__GPIO1_9,
/* Touchscreen */
CPUIMX51SD_GPIO_3_12, /* IRQ */
/* IRQ */
_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
};
static const struct imxuart_platform_data uart_pdata __initconst = {
......
arch/arm/mach-mx5/board-mx51_3ds.c
View file @ ee1ae4d7
......@@ -50,7 +50,7 @@ static iomux_v3_cfg_t mx51_3ds_pads[] = {
MX51_PAD_EIM_D27__UART3_RTS,
/* CPLD PARENT IRQ PIN */
MX51_PAD_GPIO_1_6__GPIO_1_6,
MX51_PAD_GPIO1_6__GPIO1_6,
/* KPP */
MX51_PAD_KEY_ROW0__KEY_ROW0,
......@@ -68,7 +68,7 @@ static iomux_v3_cfg_t mx51_3ds_pads[] = {
MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
MX51_PAD_NANDF_RB3__ECSPI2_MISO,
MX51_PAD_NANDF_D15__ECSPI2_MOSI,
MX51_PAD_NANDF_D12__GPIO_3_28,
MX51_PAD_NANDF_D12__GPIO3_28,
};
/* Serial ports */
......
arch/arm/mach-mx5/board-mx51_babbage.c
View file @ ee1ae4d7
......@@ -95,8 +95,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
MX51_PAD_KEY_COL5__I2C2_SDA,
/* HSI2C */
MX51_PAD_I2C1_CLK__HSI2C_CLK,
MX51_PAD_I2C1_DAT__HSI2C_DAT,
MX51_PAD_I2C1_CLK__I2C1_CLK,
MX51_PAD_I2C1_DAT__I2C1_DAT,
/* USB HOST1 */
MX51_PAD_USBH1_CLK__USBH1_CLK,
......@@ -112,29 +112,29 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
/* USB HUB reset line*/
MX51_PAD_GPIO_1_7__GPIO_1_7,
MX51_PAD_GPIO1_7__GPIO1_7,
/* FEC */
MX51_PAD_EIM_EB2__FEC_MDIO,
MX51_PAD_EIM_EB3__FEC_RDAT1,
MX51_PAD_EIM_CS2__FEC_RDAT2,
MX51_PAD_EIM_CS3__FEC_RDAT3,
MX51_PAD_EIM_EB3__FEC_RDATA1,
MX51_PAD_EIM_CS2__FEC_RDATA2,
MX51_PAD_EIM_CS3__FEC_RDATA3,
MX51_PAD_EIM_CS4__FEC_RX_ER,
MX51_PAD_EIM_CS5__FEC_CRS,
MX51_PAD_NANDF_RB2__FEC_COL,
MX51_PAD_NANDF_RB3__FEC_RXCLK,
MX51_PAD_NANDF_RB6__FEC_RDAT0,
MX51_PAD_NANDF_RB7__FEC_TDAT0,
MX51_PAD_NANDF_RB3__FEC_RX_CLK,
MX51_PAD_NANDF_D9__FEC_RDATA0,
MX51_PAD_NANDF_D8__FEC_TDATA0,
MX51_PAD_NANDF_CS2__FEC_TX_ER,
MX51_PAD_NANDF_CS3__FEC_MDC,
MX51_PAD_NANDF_CS4__FEC_TDAT1,
MX51_PAD_NANDF_CS5__FEC_TDAT2,
MX51_PAD_NANDF_CS6__FEC_TDAT3,
MX51_PAD_NANDF_CS4__FEC_TDATA1,
MX51_PAD_NANDF_CS5__FEC_TDATA2,
MX51_PAD_NANDF_CS6__FEC_TDATA3,
MX51_PAD_NANDF_CS7__FEC_TX_EN,
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
/* FEC PHY reset line */
MX51_PAD_EIM_A20__GPIO_2_14,
MX51_PAD_EIM_A20__GPIO2_14,
/* SD 1 */
MX51_PAD_SD1_CMD__SD1_CMD,
......@@ -156,8 +156,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
MX51_PAD_CSPI1_SS0__GPIO_4_24,
MX51_PAD_CSPI1_SS1__GPIO_4_25,
MX51_PAD_CSPI1_SS0__GPIO4_24,
MX51_PAD_CSPI1_SS1__GPIO4_25,
};
/* Serial ports */
......@@ -188,8 +188,8 @@ static struct imxi2c_platform_data babbage_hsi2c_data = {
static int gpio_usbh1_active(void)
{
iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5;
int ret;
/* Set USBH1_STP to GPIO and toggle it */
......@@ -352,8 +352,8 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
static void __init mxc_board_init(void)
{
iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
iomux_v3_cfg_t power_key = (MX51_PAD_EIM_A27__GPIO_2_21 &
~MUX_PAD_CTRL_MASK) | MX51_GPIO_PAD_CTRL_2;
iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
#if defined(CONFIG_CPU_FREQ_IMX)
get_cpu_op = mx51_get_cpu_op;
......
arch/arm/mach-mx5/board-mx51_efikamx.c
View file @ ee1ae4d7
......@@ -94,15 +94,15 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = {
MX51_PAD_SD2_DATA3__SD2_DATA3,
/* SD/MMC WP/CD */
MX51_PAD_GPIO_1_0__ESDHC1_CD,
MX51_PAD_GPIO_1_1__ESDHC1_WP,
MX51_PAD_GPIO_1_7__ESDHC2_WP,
MX51_PAD_GPIO_1_8__ESDHC2_CD,
MX51_PAD_GPIO1_0__SD1_CD,
MX51_PAD_GPIO1_1__SD1_WP,
MX51_PAD_GPIO1_7__SD2_WP,
MX51_PAD_GPIO1_8__SD2_CD,
/* leds */
MX51_PAD_CSI1_D9__GPIO_3_13,
MX51_PAD_CSI1_VSYNC__GPIO_3_14,
MX51_PAD_CSI1_HSYNC__GPIO_3_15,
MX51_PAD_CSI1_D9__GPIO3_13,
MX51_PAD_CSI1_VSYNC__GPIO3_14,
MX51_PAD_CSI1_HSYNC__GPIO3_15,
/* power key */
MX51_PAD_PWRKEY,
......@@ -110,14 +110,14 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = {
/* spi */
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
MX51_PAD_CSPI1_SS0__GPIO_4_24,
MX51_PAD_CSPI1_SS1__GPIO_4_25,
MX51_PAD_CSPI1_SS0__GPIO4_24,
MX51_PAD_CSPI1_SS1__GPIO4_25,
MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
/* reset */
MX51_PAD_DI1_PIN13__GPIO_3_2,
MX51_PAD_GPIO_1_4__GPIO_1_4,
MX51_PAD_DI1_PIN13__GPIO3_2,
MX51_PAD_GPIO1_4__GPIO1_4,
};
/* Serial ports */
......
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View file @ ee1ae4d7
......@@ -96,13 +96,13 @@ static iomux_v3_cfg_t mbimx51_pads[] = {
MX51_PAD_KEY_COL5__UART3_CTS,
/* TSC2007 IRQ */
MX51_PAD_NANDF_D10__GPIO_3_30,
MX51_PAD_NANDF_D10__GPIO3_30,
/* LEDS */
MX51_PAD_DISPB2_SER_DIN__GPIO_3_5,
MX51_PAD_DISPB2_SER_DIO__GPIO_3_6,
MX51_PAD_DISPB2_SER_CLK__GPIO_3_7,
MX51_PAD_DISPB2_SER_RS__GPIO_3_8,
MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
MX51_PAD_DISPB2_SER_RS__GPIO3_8,
/* KPP */
MX51_PAD_KEY_ROW0__KEY_ROW0,
......
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
View file @ ee1ae4d7
......@@ -45,14 +45,13 @@
#include "devices-imx51.h"
#include "devices.h"
#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \
MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
/* LED */
MX51_PAD_NANDF_D10__GPIO_3_30,
MX51_PAD_NANDF_D10__GPIO3_30,
/* SWITCH */
MBIMXSD_GPIO_3_31,
_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
/* UART2 */
MX51_PAD_UART2_RXD__UART2_RXD,
MX51_PAD_UART2_TXD__UART2_TXD,
......
arch/arm/plat-mxc/include/mach/iomux-mx51.h
View file @ ee1ae4d7
This source diff could not be displayed because it is too large. You can view the blob instead.
arch/arm/plat-mxc/include/mach/iomux-v3.h
View file @ ee1ae4d7
......@@ -70,6 +70,8 @@ typedef u64 iomux_v3_cfg_t;
#define MUX_SEL_INPUT_SHIFT 58
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
_sel_input, _pad_ctrl) \
(((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
......
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