Commit f03b8a54 authored by David S. Miller's avatar David S. Miller

[SPARC64]: Use different cache sizing defaults on SUN4V.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 329c68b2
...@@ -200,7 +200,8 @@ void __init device_scan(void) ...@@ -200,7 +200,8 @@ void __init device_scan(void)
#ifndef CONFIG_SMP #ifndef CONFIG_SMP
{ {
int err, cpu_node; int err, cpu_node, def;
err = cpu_find_by_instance(0, &cpu_node, NULL); err = cpu_find_by_instance(0, &cpu_node, NULL);
if (err) { if (err) {
prom_printf("No cpu nodes, cannot continue\n"); prom_printf("No cpu nodes, cannot continue\n");
...@@ -209,21 +210,40 @@ void __init device_scan(void) ...@@ -209,21 +210,40 @@ void __init device_scan(void)
cpu_data(0).clock_tick = prom_getintdefault(cpu_node, cpu_data(0).clock_tick = prom_getintdefault(cpu_node,
"clock-frequency", "clock-frequency",
0); 0);
def = ((tlb_type == hypervisor) ?
(8 * 1024) :
(16 * 1024));
cpu_data(0).dcache_size = prom_getintdefault(cpu_node, cpu_data(0).dcache_size = prom_getintdefault(cpu_node,
"dcache-size", "dcache-size",
16 * 1024); def);
def = 32;
cpu_data(0).dcache_line_size = cpu_data(0).dcache_line_size =
prom_getintdefault(cpu_node, "dcache-line-size", 32); prom_getintdefault(cpu_node, "dcache-line-size",
def);
def = 16 * 1024;
cpu_data(0).icache_size = prom_getintdefault(cpu_node, cpu_data(0).icache_size = prom_getintdefault(cpu_node,
"icache-size", "icache-size",
16 * 1024); def);
def = 32;
cpu_data(0).icache_line_size = cpu_data(0).icache_line_size =
prom_getintdefault(cpu_node, "icache-line-size", 32); prom_getintdefault(cpu_node, "icache-line-size",
def);
def = ((tlb_type == hypervisor) ?
(3 * 1024 * 1024) :
(4 * 1024 * 1024));
cpu_data(0).ecache_size = prom_getintdefault(cpu_node, cpu_data(0).ecache_size = prom_getintdefault(cpu_node,
"ecache-size", "ecache-size",
4 * 1024 * 1024); def);
def = 64;
cpu_data(0).ecache_line_size = cpu_data(0).ecache_line_size =
prom_getintdefault(cpu_node, "ecache-line-size", 64); prom_getintdefault(cpu_node, "ecache-line-size",
def);
printk("CPU[0]: Caches " printk("CPU[0]: Caches "
"D[sz(%d):line_sz(%d)] " "D[sz(%d):line_sz(%d)] "
"I[sz(%d):line_sz(%d)] " "I[sz(%d):line_sz(%d)] "
......
...@@ -78,7 +78,7 @@ void smp_bogo(struct seq_file *m) ...@@ -78,7 +78,7 @@ void smp_bogo(struct seq_file *m)
void __init smp_store_cpu_info(int id) void __init smp_store_cpu_info(int id)
{ {
int cpu_node; int cpu_node, def;
/* multiplier and counter set by /* multiplier and counter set by
smp_setup_percpu_timer() */ smp_setup_percpu_timer() */
...@@ -90,18 +90,32 @@ void __init smp_store_cpu_info(int id) ...@@ -90,18 +90,32 @@ void __init smp_store_cpu_info(int id)
cpu_data(id).idle_volume = 1; cpu_data(id).idle_volume = 1;
def = ((tlb_type == hypervisor) ? (8 * 1024) : (16 * 1024));
cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size", cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
16 * 1024); def);
def = 32;
cpu_data(id).dcache_line_size = cpu_data(id).dcache_line_size =
prom_getintdefault(cpu_node, "dcache-line-size", 32); prom_getintdefault(cpu_node, "dcache-line-size", def);
def = 16 * 1024;
cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size", cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
16 * 1024); def);
def = 32;
cpu_data(id).icache_line_size = cpu_data(id).icache_line_size =
prom_getintdefault(cpu_node, "icache-line-size", 32); prom_getintdefault(cpu_node, "icache-line-size", def);
def = ((tlb_type == hypervisor) ?
(3 * 1024 * 1024) :
(4 * 1024 * 1024));
cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size", cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
4 * 1024 * 1024); def);
def = 64;
cpu_data(id).ecache_line_size = cpu_data(id).ecache_line_size =
prom_getintdefault(cpu_node, "ecache-line-size", 64); prom_getintdefault(cpu_node, "ecache-line-size", def);
printk("CPU[%d]: Caches " printk("CPU[%d]: Caches "
"D[sz(%d):line_sz(%d)] " "D[sz(%d):line_sz(%d)] "
"I[sz(%d):line_sz(%d)] " "I[sz(%d):line_sz(%d)] "
......
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