Commit f13cc6bd authored by Rakesh Pillai's avatar Rakesh Pillai Committed by Kalle Valo

ath10k: Add hw param for 64-bit address support

WCN3990 target supports 37-bit addressing mode. In order
to accommodate extended address support, add hw param to
indicate if the target supports addressing above 32-bits.
Signed-off-by: default avatarRakesh Pillai <pillair@qti.qualcomm.com>
Signed-off-by: default avatarGovind Singh <govinds@qti.qualcomm.com>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent 203dab83
...@@ -78,6 +78,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -78,6 +78,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA9887_HW_1_0_VERSION, .id = QCA9887_HW_1_0_VERSION,
...@@ -105,6 +106,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -105,6 +106,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA6174_HW_2_1_VERSION, .id = QCA6174_HW_2_1_VERSION,
...@@ -131,6 +133,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -131,6 +133,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA6174_HW_2_1_VERSION, .id = QCA6174_HW_2_1_VERSION,
...@@ -157,6 +160,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -157,6 +160,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA6174_HW_3_0_VERSION, .id = QCA6174_HW_3_0_VERSION,
...@@ -183,6 +187,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -183,6 +187,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA6174_HW_3_2_VERSION, .id = QCA6174_HW_3_2_VERSION,
...@@ -212,6 +217,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -212,6 +217,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA99X0_HW_2_0_DEV_VERSION, .id = QCA99X0_HW_2_0_DEV_VERSION,
...@@ -244,6 +250,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -244,6 +250,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA9984_HW_1_0_DEV_VERSION, .id = QCA9984_HW_1_0_DEV_VERSION,
...@@ -281,6 +288,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -281,6 +288,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA9888_HW_2_0_DEV_VERSION, .id = QCA9888_HW_2_0_DEV_VERSION,
...@@ -317,6 +325,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -317,6 +325,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA9377_HW_1_0_DEV_VERSION, .id = QCA9377_HW_1_0_DEV_VERSION,
...@@ -343,6 +352,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -343,6 +352,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA9377_HW_1_1_DEV_VERSION, .id = QCA9377_HW_1_1_DEV_VERSION,
...@@ -371,6 +381,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -371,6 +381,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = QCA4019_HW_1_0_DEV_VERSION, .id = QCA4019_HW_1_0_DEV_VERSION,
...@@ -404,6 +415,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -404,6 +415,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_TLV_NUM_PEERS, .num_peers = TARGET_TLV_NUM_PEERS,
.ast_skid_limit = 0x10, .ast_skid_limit = 0x10,
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false,
}, },
{ {
.id = WCN3990_HW_1_0_DEV_VERSION, .id = WCN3990_HW_1_0_DEV_VERSION,
...@@ -422,6 +434,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -422,6 +434,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_peers = TARGET_HL_10_TLV_NUM_PEERS, .num_peers = TARGET_HL_10_TLV_NUM_PEERS,
.ast_skid_limit = TARGET_HL_10_TLV_AST_SKID_LIMIT, .ast_skid_limit = TARGET_HL_10_TLV_AST_SKID_LIMIT,
.num_wds_entries = TARGET_HL_10_TLV_NUM_WDS_ENTRIES, .num_wds_entries = TARGET_HL_10_TLV_NUM_WDS_ENTRIES,
.target_64bit = true,
}, },
}; };
......
...@@ -561,6 +561,9 @@ struct ath10k_hw_params { ...@@ -561,6 +561,9 @@ struct ath10k_hw_params {
u32 num_peers; u32 num_peers;
u32 ast_skid_limit; u32 ast_skid_limit;
u32 num_wds_entries; u32 num_wds_entries;
/* Targets supporting physical addressing capability above 32-bits */
bool target_64bit;
}; };
struct htt_rx_desc; struct htt_rx_desc;
......
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