Commit f2405db8 authored by Don Brace's avatar Don Brace Committed by James Bottomley

hpsa: do not queue commands internally in driver

By not doing maintaining a list of queued commands, we can eliminate some spin
locking in the main i/o path and gain significant improvement in IOPS.  Remove
the queuing code and the code that calls it; remove now-unused interrupt code;
remove DIRECT_LOOKUP_BIT.

Now that the passthru commands share the same command pool as
the main i/o path, and the total size of the pool is less than
or equal to the number of commands that will fit in the hardware
fifo, there is no need to check to see if we are exceeding the
hardware fifo's depth.
Reviewed-by: default avatarScott Teel <scott.teel@pmcs.com>
Reviewed-by: default avatarRobert Elliott <elliott@hp.com>
Signed-off-by: default avatarDon Brace <don.brace@pmcs.com>
Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
parent 45fcb86e
This diff is collapsed.
...@@ -32,7 +32,6 @@ struct access_method { ...@@ -32,7 +32,6 @@ struct access_method {
void (*submit_command)(struct ctlr_info *h, void (*submit_command)(struct ctlr_info *h,
struct CommandList *c); struct CommandList *c);
void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
unsigned long (*fifo_full)(struct ctlr_info *h);
bool (*intr_pending)(struct ctlr_info *h); bool (*intr_pending)(struct ctlr_info *h);
unsigned long (*command_completed)(struct ctlr_info *h, u8 q); unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
}; };
...@@ -133,8 +132,6 @@ struct ctlr_info { ...@@ -133,8 +132,6 @@ struct ctlr_info {
char hba_mode_enabled; char hba_mode_enabled;
/* queue and queue Info */ /* queue and queue Info */
struct list_head reqQ;
struct list_head cmpQ;
unsigned int Qdepth; unsigned int Qdepth;
unsigned int maxSG; unsigned int maxSG;
spinlock_t lock; spinlock_t lock;
...@@ -197,7 +194,6 @@ struct ctlr_info { ...@@ -197,7 +194,6 @@ struct ctlr_info {
u32 __percpu *lockup_detected; u32 __percpu *lockup_detected;
struct delayed_work monitor_ctlr_work; struct delayed_work monitor_ctlr_work;
int remove_in_progress; int remove_in_progress;
u32 fifo_recently_full;
/* Address of h->q[x] is passed to intr handler to know which queue */ /* Address of h->q[x] is passed to intr handler to know which queue */
u8 q[MAX_REPLY_QUEUES]; u8 q[MAX_REPLY_QUEUES];
u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
...@@ -427,14 +423,6 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) ...@@ -427,14 +423,6 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
return register_value; return register_value;
} }
/*
* Returns true if fifo is full.
*
*/
static unsigned long SA5_fifo_full(struct ctlr_info *h)
{
return atomic_read(&h->commands_outstanding) >= h->max_commands;
}
/* /*
* returns value read from hardware. * returns value read from hardware.
* returns FIFO_EMPTY if there is nothing to read * returns FIFO_EMPTY if there is nothing to read
...@@ -527,7 +515,6 @@ static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) ...@@ -527,7 +515,6 @@ static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
static struct access_method SA5_access = { static struct access_method SA5_access = {
SA5_submit_command, SA5_submit_command,
SA5_intr_mask, SA5_intr_mask,
SA5_fifo_full,
SA5_intr_pending, SA5_intr_pending,
SA5_completed, SA5_completed,
}; };
...@@ -535,7 +522,6 @@ static struct access_method SA5_access = { ...@@ -535,7 +522,6 @@ static struct access_method SA5_access = {
static struct access_method SA5_ioaccel_mode1_access = { static struct access_method SA5_ioaccel_mode1_access = {
SA5_submit_command, SA5_submit_command,
SA5_performant_intr_mask, SA5_performant_intr_mask,
SA5_fifo_full,
SA5_ioaccel_mode1_intr_pending, SA5_ioaccel_mode1_intr_pending,
SA5_ioaccel_mode1_completed, SA5_ioaccel_mode1_completed,
}; };
...@@ -543,7 +529,6 @@ static struct access_method SA5_ioaccel_mode1_access = { ...@@ -543,7 +529,6 @@ static struct access_method SA5_ioaccel_mode1_access = {
static struct access_method SA5_ioaccel_mode2_access = { static struct access_method SA5_ioaccel_mode2_access = {
SA5_submit_command_ioaccel2, SA5_submit_command_ioaccel2,
SA5_performant_intr_mask, SA5_performant_intr_mask,
SA5_fifo_full,
SA5_performant_intr_pending, SA5_performant_intr_pending,
SA5_performant_completed, SA5_performant_completed,
}; };
...@@ -551,7 +536,6 @@ static struct access_method SA5_ioaccel_mode2_access = { ...@@ -551,7 +536,6 @@ static struct access_method SA5_ioaccel_mode2_access = {
static struct access_method SA5_performant_access = { static struct access_method SA5_performant_access = {
SA5_submit_command, SA5_submit_command,
SA5_performant_intr_mask, SA5_performant_intr_mask,
SA5_fifo_full,
SA5_performant_intr_pending, SA5_performant_intr_pending,
SA5_performant_completed, SA5_performant_completed,
}; };
...@@ -559,7 +543,6 @@ static struct access_method SA5_performant_access = { ...@@ -559,7 +543,6 @@ static struct access_method SA5_performant_access = {
static struct access_method SA5_performant_access_no_read = { static struct access_method SA5_performant_access_no_read = {
SA5_submit_command_no_read, SA5_submit_command_no_read,
SA5_performant_intr_mask, SA5_performant_intr_mask,
SA5_fifo_full,
SA5_performant_intr_pending, SA5_performant_intr_pending,
SA5_performant_completed, SA5_performant_completed,
}; };
......
...@@ -375,22 +375,19 @@ struct ErrorInfo { ...@@ -375,22 +375,19 @@ struct ErrorInfo {
#define CMD_IOACCEL1 0x04 #define CMD_IOACCEL1 0x04
#define CMD_IOACCEL2 0x05 #define CMD_IOACCEL2 0x05
#define DIRECT_LOOKUP_SHIFT 5 #define DIRECT_LOOKUP_SHIFT 4
#define DIRECT_LOOKUP_BIT 0x10
#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
#define HPSA_ERROR_BIT 0x02 #define HPSA_ERROR_BIT 0x02
struct ctlr_info; /* defined in hpsa.h */ struct ctlr_info; /* defined in hpsa.h */
/* The size of this structure needs to be divisible by 32 /* The size of this structure needs to be divisible by 128
* on all architectures because low 5 bits of the addresses * on all architectures. The low 4 bits of the addresses
* are used as follows: * are used as follows:
* *
* bit 0: to device, used to indicate "performant mode" command * bit 0: to device, used to indicate "performant mode" command
* from device, indidcates error status. * from device, indidcates error status.
* bit 1-3: to device, indicates block fetch table entry for * bit 1-3: to device, indicates block fetch table entry for
* reducing DMA in fetching commands from host memory. * reducing DMA in fetching commands from host memory.
* bit 4: used to indicate whether tag is "direct lookup" (index),
* or a bus address.
*/ */
#define COMMANDLIST_ALIGNMENT 128 #define COMMANDLIST_ALIGNMENT 128
...@@ -405,7 +402,6 @@ struct CommandList { ...@@ -405,7 +402,6 @@ struct CommandList {
struct ctlr_info *h; struct ctlr_info *h;
int cmd_type; int cmd_type;
long cmdindex; long cmdindex;
struct list_head list;
struct completion *waiting; struct completion *waiting;
void *scsi_cmd; void *scsi_cmd;
} __aligned(COMMANDLIST_ALIGNMENT); } __aligned(COMMANDLIST_ALIGNMENT);
......
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