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Commit f65e4fa8 authored by Ralf Baechle's avatar Ralf Baechle
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[MIPS] Improve branch prediction in ll/sc atomic operations. 

Now that finally all supported versions of binutils have functioning
support for .subsection use .subsection to tweak the branch prediction

I did not modify the R10000 errata variants because it seems unclear if
this will invalidate the workaround which actually relies on the cheesy
prediction of branch likely to cause a misspredict if the sc was
successful.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 509cb37e
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Showing with 127 additions and 32 deletions
include/asm-mips/atomic.h
View file @ f65e4fa8
...@@ -69,7 +69,10 @@ static __inline__ void atomic_add(int i, atomic_t * v) ...@@ -69,7 +69,10 @@ static __inline__ void atomic_add(int i, atomic_t * v)
"1: ll %0, %1 # atomic_add \n" "1: ll %0, %1 # atomic_add \n"
" addu %0, %2 \n" " addu %0, %2 \n"
" sc %0, %1 \n" " sc %0, %1 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (temp), "=m" (v->counter) : "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)); : "Ir" (i), "m" (v->counter));
...@@ -111,7 +114,10 @@ static __inline__ void atomic_sub(int i, atomic_t * v) ...@@ -111,7 +114,10 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
"1: ll %0, %1 # atomic_sub \n" "1: ll %0, %1 # atomic_sub \n"
" subu %0, %2 \n" " subu %0, %2 \n"
" sc %0, %1 \n" " sc %0, %1 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (temp), "=m" (v->counter) : "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)); : "Ir" (i), "m" (v->counter));
...@@ -155,8 +161,11 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) ...@@ -155,8 +161,11 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
"1: ll %1, %2 # atomic_add_return \n" "1: ll %1, %2 # atomic_add_return \n"
" addu %0, %1, %3 \n" " addu %0, %1, %3 \n"
" sc %0, %2 \n" " sc %0, %2 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" addu %0, %1, %3 \n" " addu %0, %1, %3 \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter) : "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter) : "Ir" (i), "m" (v->counter)
...@@ -204,8 +213,11 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) ...@@ -204,8 +213,11 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
"1: ll %1, %2 # atomic_sub_return \n" "1: ll %1, %2 # atomic_sub_return \n"
" subu %0, %1, %3 \n" " subu %0, %1, %3 \n"
" sc %0, %2 \n" " sc %0, %2 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" subu %0, %1, %3 \n" " subu %0, %1, %3 \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter) : "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter) : "Ir" (i), "m" (v->counter)
...@@ -267,10 +279,13 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) ...@@ -267,10 +279,13 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
" bltz %0, 1f \n" " bltz %0, 1f \n"
" sc %0, %2 \n" " sc %0, %2 \n"
" .set noreorder \n" " .set noreorder \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" subu %0, %1, %3 \n" " subu %0, %1, %3 \n"
" .set reorder \n" " .set reorder \n"
"1: \n" "1: \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter) : "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter) : "Ir" (i), "m" (v->counter)
...@@ -429,7 +444,10 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) ...@@ -429,7 +444,10 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
"1: lld %0, %1 # atomic64_add \n" "1: lld %0, %1 # atomic64_add \n"
" addu %0, %2 \n" " addu %0, %2 \n"
" scd %0, %1 \n" " scd %0, %1 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (temp), "=m" (v->counter) : "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)); : "Ir" (i), "m" (v->counter));
...@@ -471,7 +489,10 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) ...@@ -471,7 +489,10 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
"1: lld %0, %1 # atomic64_sub \n" "1: lld %0, %1 # atomic64_sub \n"
" subu %0, %2 \n" " subu %0, %2 \n"
" scd %0, %1 \n" " scd %0, %1 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (temp), "=m" (v->counter) : "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)); : "Ir" (i), "m" (v->counter));
...@@ -515,8 +536,11 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) ...@@ -515,8 +536,11 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
"1: lld %1, %2 # atomic64_add_return \n" "1: lld %1, %2 # atomic64_add_return \n"
" addu %0, %1, %3 \n" " addu %0, %1, %3 \n"
" scd %0, %2 \n" " scd %0, %2 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" addu %0, %1, %3 \n" " addu %0, %1, %3 \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter) : "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter) : "Ir" (i), "m" (v->counter)
...@@ -564,8 +588,11 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) ...@@ -564,8 +588,11 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
"1: lld %1, %2 # atomic64_sub_return \n" "1: lld %1, %2 # atomic64_sub_return \n"
" subu %0, %1, %3 \n" " subu %0, %1, %3 \n"
" scd %0, %2 \n" " scd %0, %2 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" subu %0, %1, %3 \n" " subu %0, %1, %3 \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter) : "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter) : "Ir" (i), "m" (v->counter)
...@@ -627,10 +654,13 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) ...@@ -627,10 +654,13 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
" bltz %0, 1f \n" " bltz %0, 1f \n"
" scd %0, %2 \n" " scd %0, %2 \n"
" .set noreorder \n" " .set noreorder \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" dsubu %0, %1, %3 \n" " dsubu %0, %1, %3 \n"
" .set reorder \n" " .set reorder \n"
"1: \n" "1: \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter) : "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter) : "Ir" (i), "m" (v->counter)
......
include/asm-mips/bitops.h
View file @ f65e4fa8
...@@ -68,7 +68,10 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) ...@@ -68,7 +68,10 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
"1: " __LL "%0, %1 # set_bit \n" "1: " __LL "%0, %1 # set_bit \n"
" or %0, %2 \n" " or %0, %2 \n"
" " __SC "%0, %1 \n" " " __SC "%0, %1 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (temp), "=m" (*m) : "=&r" (temp), "=m" (*m)
: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
...@@ -116,7 +119,10 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) ...@@ -116,7 +119,10 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
"1: " __LL "%0, %1 # clear_bit \n" "1: " __LL "%0, %1 # clear_bit \n"
" and %0, %2 \n" " and %0, %2 \n"
" " __SC "%0, %1 \n" " " __SC "%0, %1 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (temp), "=m" (*m) : "=&r" (temp), "=m" (*m)
: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
...@@ -166,7 +172,10 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) ...@@ -166,7 +172,10 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
"1: " __LL "%0, %1 # change_bit \n" "1: " __LL "%0, %1 # change_bit \n"
" xor %0, %2 \n" " xor %0, %2 \n"
" " __SC "%0, %1 \n" " " __SC "%0, %1 \n"
" beqz %0, 1b \n" " beqz %0, 2f \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (temp), "=m" (*m) : "=&r" (temp), "=m" (*m)
: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
...@@ -222,8 +231,12 @@ static inline int test_and_set_bit(unsigned long nr, ...@@ -222,8 +231,12 @@ static inline int test_and_set_bit(unsigned long nr,
"1: " __LL "%0, %1 # test_and_set_bit \n" "1: " __LL "%0, %1 # test_and_set_bit \n"
" or %2, %0, %3 \n" " or %2, %0, %3 \n"
" " __SC "%2, %1 \n" " " __SC "%2, %1 \n"
" beqz %2, 1b \n" " beqz %2, 2f \n"
" and %2, %0, %3 \n" " and %2, %0, %3 \n"
" .subsection 2 \n"
"2: b 1b \n"
" nop \n"
" .previous \n"
" .set pop \n" " .set pop \n"
: "=&r" (temp), "=m" (*m), "=&r" (res) : "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
...@@ -290,8 +303,12 @@ static inline int test_and_clear_bit(unsigned long nr, ...@@ -290,8 +303,12 @@ static inline int test_and_clear_bit(unsigned long nr,
" or %2, %0, %3 \n" " or %2, %0, %3 \n"
" xor %2, %3 \n" " xor %2, %3 \n"
" " __SC "%2, %1 \n" " " __SC "%2, %1 \n"
" beqz %2, 1b \n" " beqz %2, 2f \n"
" and %2, %0, %3 \n" " and %2, %0, %3 \n"
" .subsection 2 \n"
"2: b 1b \n"
" nop \n"
" .previous \n"
" .set pop \n" " .set pop \n"
: "=&r" (temp), "=m" (*m), "=&r" (res) : "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
...@@ -356,8 +373,12 @@ static inline int test_and_change_bit(unsigned long nr, ...@@ -356,8 +373,12 @@ static inline int test_and_change_bit(unsigned long nr,
"1: " __LL "%0, %1 # test_and_change_bit \n" "1: " __LL "%0, %1 # test_and_change_bit \n"
" xor %2, %0, %3 \n" " xor %2, %0, %3 \n"
" " __SC "\t%2, %1 \n" " " __SC "\t%2, %1 \n"
" beqz %2, 1b \n" " beqz %2, 2f \n"
" and %2, %0, %3 \n" " and %2, %0, %3 \n"
" .subsection 2 \n"
"2: b 1b \n"
" nop \n"
" .previous \n"
" .set pop \n" " .set pop \n"
: "=&r" (temp), "=m" (*m), "=&r" (res) : "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
......
include/asm-mips/spinlock.h
View file @ f65e4fa8
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
* *
* Copyright (C) 1999, 2000, 06 by Ralf Baechle * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/ */
#ifndef _ASM_SPINLOCK_H #ifndef _ASM_SPINLOCK_H
...@@ -49,11 +49,18 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) ...@@ -49,11 +49,18 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
__asm__ __volatile__( __asm__ __volatile__(
" .set noreorder # __raw_spin_lock \n" " .set noreorder # __raw_spin_lock \n"
"1: ll %1, %2 \n" "1: ll %1, %2 \n"
" bnez %1, 1b \n" " bnez %1, 2f \n"
" li %1, 1 \n" " li %1, 1 \n"
" sc %1, %0 \n" " sc %1, %0 \n"
" beqz %1, 1b \n" " beqz %1, 2f \n"
" nop \n" " nop \n"
" .subsection 2 \n"
"2: ll %1, %2 \n"
" bnez %1, 2b \n"
" li %1, 1 \n"
" b 1b \n"
" nop \n"
" .previous \n"
" .set reorder \n" " .set reorder \n"
: "=m" (lock->lock), "=&r" (tmp) : "=m" (lock->lock), "=&r" (tmp)
: "m" (lock->lock) : "m" (lock->lock)
...@@ -99,8 +106,12 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) ...@@ -99,8 +106,12 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
"1: ll %0, %3 \n" "1: ll %0, %3 \n"
" ori %2, %0, 1 \n" " ori %2, %0, 1 \n"
" sc %2, %1 \n" " sc %2, %1 \n"
" beqz %2, 1b \n" " beqz %2, 2f \n"
" andi %2, %0, 1 \n" " andi %2, %0, 1 \n"
" .subsection 2 \n"
"2: b 1b \n"
" nop \n"
" .previous \n"
" .set reorder" " .set reorder"
: "=&r" (temp), "=m" (lock->lock), "=&r" (res) : "=&r" (temp), "=m" (lock->lock), "=&r" (res)
: "m" (lock->lock) : "m" (lock->lock)
...@@ -154,11 +165,18 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) ...@@ -154,11 +165,18 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
__asm__ __volatile__( __asm__ __volatile__(
" .set noreorder # __raw_read_lock \n" " .set noreorder # __raw_read_lock \n"
"1: ll %1, %2 \n" "1: ll %1, %2 \n"
" bltz %1, 1b \n" " bltz %1, 2f \n"
" addu %1, 1 \n" " addu %1, 1 \n"
" sc %1, %0 \n" " sc %1, %0 \n"
" beqz %1, 1b \n" " beqz %1, 1b \n"
" nop \n" " nop \n"
" .subsection 2 \n"
"2: ll %1, %2 \n"
" bltz %1, 2b \n"
" addu %1, 1 \n"
" b 1b \n"
" nop \n"
" .previous \n"
" .set reorder \n" " .set reorder \n"
: "=m" (rw->lock), "=&r" (tmp) : "=m" (rw->lock), "=&r" (tmp)
: "m" (rw->lock) : "m" (rw->lock)
...@@ -192,8 +210,12 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) ...@@ -192,8 +210,12 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
"1: ll %1, %2 \n" "1: ll %1, %2 \n"
" sub %1, 1 \n" " sub %1, 1 \n"
" sc %1, %0 \n" " sc %1, %0 \n"
" beqz %1, 1b \n" " beqz %1, 2f \n"
" nop \n"
" .subsection 2 \n"
"2: b 1b \n"
" nop \n" " nop \n"
" .previous \n"
" .set reorder \n" " .set reorder \n"
: "=m" (rw->lock), "=&r" (tmp) : "=m" (rw->lock), "=&r" (tmp)
: "m" (rw->lock) : "m" (rw->lock)
...@@ -222,11 +244,18 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) ...@@ -222,11 +244,18 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
__asm__ __volatile__( __asm__ __volatile__(
" .set noreorder # __raw_write_lock \n" " .set noreorder # __raw_write_lock \n"
"1: ll %1, %2 \n" "1: ll %1, %2 \n"
" bnez %1, 1b \n" " bnez %1, 2f \n"
" lui %1, 0x8000 \n" " lui %1, 0x8000 \n"
" sc %1, %0 \n" " sc %1, %0 \n"
" beqz %1, 1b \n" " beqz %1, 2f \n"
" nop \n"
" .subsection 2 \n"
"2: ll %1, %2 \n"
" bnez %1, 2b \n"
" lui %1, 0x8000 \n"
" b 1b \n"
" nop \n" " nop \n"
" .previous \n"
" .set reorder \n" " .set reorder \n"
: "=m" (rw->lock), "=&r" (tmp) : "=m" (rw->lock), "=&r" (tmp)
: "m" (rw->lock) : "m" (rw->lock)
...@@ -322,12 +351,15 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) ...@@ -322,12 +351,15 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
" bnez %1, 2f \n" " bnez %1, 2f \n"
" lui %1, 0x8000 \n" " lui %1, 0x8000 \n"
" sc %1, %0 \n" " sc %1, %0 \n"
" beqz %1, 1b \n" " beqz %1, 3f \n"
" nop \n" " li %2, 1 \n"
"2: \n"
__WEAK_ORDERING_MB __WEAK_ORDERING_MB
" li %2, 1 \n" " .subsection 2 \n"
"3: b 1b \n"
" li %2, 0 \n"
" .previous \n"
" .set reorder \n" " .set reorder \n"
"2: \n"
: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
: "m" (rw->lock) : "m" (rw->lock)
: "memory"); : "memory");
......
include/asm-mips/system.h
View file @ f65e4fa8
...@@ -110,7 +110,10 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) ...@@ -110,7 +110,10 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
" move %2, %z4 \n" " move %2, %z4 \n"
" .set mips3 \n" " .set mips3 \n"
" sc %2, %1 \n" " sc %2, %1 \n"
" beqz %2, 1b \n" " beqz %2, 2f \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy) : "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val) : "R" (*m), "Jr" (val)
...@@ -155,7 +158,10 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) ...@@ -155,7 +158,10 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
"1: lld %0, %3 # xchg_u64 \n" "1: lld %0, %3 # xchg_u64 \n"
" move %2, %z4 \n" " move %2, %z4 \n"
" scd %2, %1 \n" " scd %2, %1 \n"
" beqz %2, 1b \n" " beqz %2, 2f \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
" .set mips0 \n" " .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy) : "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val) : "R" (*m), "Jr" (val)
...@@ -232,8 +238,11 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, ...@@ -232,8 +238,11 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
" move $1, %z4 \n" " move $1, %z4 \n"
" .set mips3 \n" " .set mips3 \n"
" sc $1, %1 \n" " sc $1, %1 \n"
" beqz $1, 1b \n" " beqz $1, 3f \n"
"2: \n" "2: \n"
" .subsection 2 \n"
"3: b 1b \n"
" .previous \n"
" .set pop \n" " .set pop \n"
: "=&r" (retval), "=R" (*m) : "=&r" (retval), "=R" (*m)
: "R" (*m), "Jr" (old), "Jr" (new) : "R" (*m), "Jr" (old), "Jr" (new)
...@@ -283,8 +292,11 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, ...@@ -283,8 +292,11 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
" bne %0, %z3, 2f \n" " bne %0, %z3, 2f \n"
" move $1, %z4 \n" " move $1, %z4 \n"
" scd $1, %1 \n" " scd $1, %1 \n"
" beqz $1, 1b \n" " beqz $1, 3f \n"
"2: \n" "2: \n"
" .subsection 2 \n"
"3: b 1b \n"
" .previous \n"
" .set pop \n" " .set pop \n"
: "=&r" (retval), "=R" (*m) : "=&r" (retval), "=R" (*m)
: "R" (*m), "Jr" (old), "Jr" (new) : "R" (*m), "Jr" (old), "Jr" (new)
......
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