Commit f92c710f authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo

ARM: imx: Remove remnant board file support pieces

Since i.MX board files are gone, remove some remnant pieces of
board file support.
Signed-off-by: default avatarFabio Estevam <festevam@gmail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 8485adf1
...@@ -5,7 +5,7 @@ obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o ...@@ -5,7 +5,7 @@ obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o iomux-imx31.o mach-imx31.o obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o
imx5-pm-$(CONFIG_PM) += pm-imx5.o imx5-pm-$(CONFIG_PM) += pm-imx5.o
......
...@@ -17,23 +17,14 @@ struct device_node; ...@@ -17,23 +17,14 @@ struct device_node;
enum mxc_cpu_pwr_mode; enum mxc_cpu_pwr_mode;
struct of_device_id; struct of_device_id;
void mx21_map_io(void);
void mx31_map_io(void); void mx31_map_io(void);
void mx35_map_io(void); void mx35_map_io(void);
void imx21_init_early(void); void imx21_init_early(void);
void imx31_init_early(void); void imx31_init_early(void);
void imx35_init_early(void); void imx35_init_early(void);
void mxc_init_irq(void __iomem *); void mxc_init_irq(void __iomem *);
void mx21_init_irq(void);
void mx31_init_irq(void); void mx31_init_irq(void);
void mx35_init_irq(void); void mx35_init_irq(void);
void imx21_soc_init(void);
int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref);
int mx35_clocks_init(void);
struct platform_device *mxc_register_gpio(char *name, int id,
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
void mxc_set_cpu_type(unsigned int type); void mxc_set_cpu_type(unsigned int type);
void mxc_restart(enum reboot_mode, const char *); void mxc_restart(enum reboot_mode, const char *);
void mxc_arch_reset_init(void __iomem *); void mxc_arch_reset_init(void __iomem *);
......
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*/
#include "devices/devices-common.h"
extern const struct imx_fec_data imx27_fec_data;
#define imx27_add_fec(pdata) \
imx_add_fec(&imx27_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
#define imx27_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
extern const struct imx_imx27_coda_data imx27_coda_data;
#define imx27_add_coda() \
imx_add_imx27_coda(&imx27_coda_data)
extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
#define imx27_add_imx2_wdt() \
imx_add_imx2_wdt(&imx27_imx2_wdt_data)
extern const struct imx_imx_fb_data imx27_imx_fb_data;
#define imx27_add_imx_fb(pdata) \
imx_add_imx_fb(&imx27_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx27_imx_i2c_data[];
#define imx27_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
extern const struct imx_imx_keypad_data imx27_imx_keypad_data;
#define imx27_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx27_imx_ssi_data[];
#define imx27_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
#define imx27_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata)
#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata)
#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata)
#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata)
#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
#define imx27_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
extern const struct imx_mx2_emma_data imx27_mx2_emmaprp_data;
#define imx27_add_mx2_emmaprp() \
imx_add_mx2_emmaprp(&imx27_mx2_emmaprp_data)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
#define imx27_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[];
#define imx27_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[];
#define imx27_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
#define imx27_add_mxc_w1() \
imx_add_mxc_w1(&imx27_mxc_w1_data)
extern const struct imx_spi_imx_data imx27_cspi_data[];
#define imx27_add_cspi(id, gtable) \
imx_add_spi_imx(&imx27_cspi_data[id], gtable)
#define imx27_add_spi_imx0(gtable) imx27_add_cspi(0, gtable)
#define imx27_add_spi_imx1(gtable) imx27_add_cspi(1, gtable)
#define imx27_add_spi_imx2(gtable) imx27_add_cspi(2, gtable)
extern const struct imx_pata_imx_data imx27_pata_imx_data;
#define imx27_add_pata_imx() \
imx_add_pata_imx(&imx27_pata_imx_data)
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*/
#include "devices/devices-common.h"
extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
#define imx31_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
#define imx31_add_imx2_wdt() \
imx_add_imx2_wdt(&imx31_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
#define imx31_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata)
#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx31_imx_keypad_data;
#define imx31_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx31_imx_ssi_data[];
#define imx31_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
#define imx31_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata)
#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata)
#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
extern const struct imx_ipu_core_data imx31_ipu_core_data;
#define imx31_add_ipu_core() \
imx_add_ipu_core(&imx31_ipu_core_data)
#define imx31_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
#define imx31_add_mx3_sdc_fb(pdata) \
imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data;
#define imx31_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[];
#define imx31_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[];
#define imx31_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
#define imx31_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
#define imx31_add_mxc_rtc() \
imx_add_mxc_rtc(&imx31_mxc_rtc_data)
extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
#define imx31_add_mxc_w1() \
imx_add_mxc_w1(&imx31_mxc_w1_data)
extern const struct imx_spi_imx_data imx31_cspi_data[];
#define imx31_add_cspi(id, gtable) \
imx_add_spi_imx(&imx31_cspi_data[id], gtable)
#define imx31_add_spi_imx0(gtable) imx31_add_cspi(0, gtable)
#define imx31_add_spi_imx1(gtable) imx31_add_cspi(1, gtable)
#define imx31_add_spi_imx2(gtable) imx31_add_cspi(2, gtable)
extern const struct imx_pata_imx_data imx31_pata_imx_data;
#define imx31_add_pata_imx() \
imx_add_pata_imx(&imx31_pata_imx_data)
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*/
#include "devices/devices-common.h"
extern const struct imx_fec_data imx35_fec_data;
#define imx35_add_fec(pdata) \
imx_add_fec(&imx35_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data;
#define imx35_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
extern const struct imx_flexcan_data imx35_flexcan_data[];
#define imx35_add_flexcan(id) \
imx_add_flexcan(&imx35_flexcan_data[id])
#define imx35_add_flexcan0() imx35_add_flexcan(0)
#define imx35_add_flexcan1() imx35_add_flexcan(1)
extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
#define imx35_add_imx2_wdt() \
imx_add_imx2_wdt(&imx35_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
#define imx35_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx35_imx_keypad_data;
#define imx35_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx35_imx_ssi_data[];
#define imx35_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
#define imx35_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata)
#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
extern const struct imx_ipu_core_data imx35_ipu_core_data;
#define imx35_add_ipu_core() \
imx_add_ipu_core(&imx35_ipu_core_data)
#define imx35_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
#define imx35_add_mx3_sdc_fb(pdata) \
imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data;
#define imx35_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data;
#define imx35_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
#define imx35_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data;
#define imx35_add_mxc_rtc() \
imx_add_mxc_rtc(&imx35_mxc_rtc_data)
extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
#define imx35_add_mxc_w1() \
imx_add_mxc_w1(&imx35_mxc_w1_data)
extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
#define imx35_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx35_cspi_data[];
#define imx35_add_cspi(id, pdata) \
imx_add_spi_imx(&imx35_cspi_data[id], pdata)
#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
extern const struct imx_pata_imx_data imx35_pata_imx_data;
#define imx35_add_pata_imx() \
imx_add_pata_imx(&imx35_pata_imx_data)
...@@ -97,7 +97,6 @@ ...@@ -97,7 +97,6 @@
#include "mx31.h" #include "mx31.h"
#include "mx35.h" #include "mx35.h"
#include "mx2x.h" #include "mx2x.h"
#include "mx21.h"
#include "mx27.h" #include "mx27.h"
#define imx_map_entry(soc, name, _type) { \ #define imx_map_entry(soc, name, _type) { \
......
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
*/
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include "hardware.h"
#include "iomux-mx3.h"
/*
* IOMUX register (base) addresses
*/
#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
#define IOMUXGPR (IOMUX_BASE + 0x008)
#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
static DEFINE_SPINLOCK(gpio_mux_lock);
#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
static DECLARE_BITMAP(mxc_pin_alloc_map, NB_PORTS * 32);
/*
* set the mode for a IOMUX pin.
*/
void mxc_iomux_mode(unsigned int pin_mode)
{
u32 field;
u32 l;
u32 mode;
void __iomem *reg;
reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
field = pin_mode & 0x3;
mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
spin_lock(&gpio_mux_lock);
l = imx_readl(reg);
l &= ~(0xff << (field * 8));
l |= mode << (field * 8);
imx_writel(l, reg);
spin_unlock(&gpio_mux_lock);
}
/*
* This function configures the pad value for a IOMUX pin.
*/
void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
{
u32 field, l;
void __iomem *reg;
pin &= IOMUX_PADNUM_MASK;
reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
field = (pin + 2) % 3;
pr_debug("%s: reg offset = 0x%x, field = %d\n",
__func__, (pin + 2) / 3, field);
spin_lock(&gpio_mux_lock);
l = imx_readl(reg);
l &= ~(0x1ff << (field * 10));
l |= config << (field * 10);
imx_writel(l, reg);
spin_unlock(&gpio_mux_lock);
}
/*
* allocs a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
*/
int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
{
unsigned pad = pin & IOMUX_PADNUM_MASK;
if (pad >= (PIN_MAX + 1)) {
printk(KERN_ERR "mxc_iomux: Attempt to request nonexistent pin %u for \"%s\"\n",
pad, label ? label : "?");
return -EINVAL;
}
if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
pad, label ? label : "?");
return -EBUSY;
}
mxc_iomux_mode(pin);
return 0;
}
int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
const char *label)
{
const unsigned int *p = pin_list;
int i;
int ret = -EINVAL;
for (i = 0; i < count; i++) {
ret = mxc_iomux_alloc_pin(*p, label);
if (ret)
goto setup_error;
p++;
}
return 0;
setup_error:
mxc_iomux_release_multiple_pins(pin_list, i);
return ret;
}
void mxc_iomux_release_pin(unsigned int pin)
{
unsigned pad = pin & IOMUX_PADNUM_MASK;
if (pad < (PIN_MAX + 1))
clear_bit(pad, mxc_pin_alloc_map);
}
void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
{
const unsigned int *p = pin_list;
int i;
for (i = 0; i < count; i++) {
mxc_iomux_release_pin(*p);
p++;
}
}
/*
* This function enables/disables the general purpose function for a particular
* signal.
*/
void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
{
u32 l;
spin_lock(&gpio_mux_lock);
l = imx_readl(IOMUXGPR);
if (en)
l |= gp;
else
l &= ~gp;
imx_writel(l, IOMUXGPR);
spin_unlock(&gpio_mux_lock);
}
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
*/
#ifndef __MACH_IOMUX_MX21_H__
#define __MACH_IOMUX_MX21_H__
#include "iomux-mx2x.h"
#include "iomux-v1.h"
/* Primary GPIO pin functions */
#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22)
#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25)
#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5)
#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6)
#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7)
#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8)
#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9)
#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10)
#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11)
#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12)
#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13)
#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16)
#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17)
#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18)
#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19)
#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0)
#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1)
#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2)
#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1)
#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3)
#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7)
#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8)
#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9)
#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10)
#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11)
#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12)
#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13)
#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14)
#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16)
/* Alternate GPIO pin functions */
#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5)
#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6)
#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7)
#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8)
#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9)
#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10)
#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11)
#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12)
#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13)
#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14)
#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15)
#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16)
#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17)
#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18)
#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19)
#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20)
#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21)
#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22)
#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23)
#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29)
#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30)
/* AIN GPIO pin functions */
#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
/* BIN GPIO pin functions */
#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
/* CIN GPIO pin functions */
#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
/* AOUT GPIO pin functions */
#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
#endif /* ifndef __MACH_IOMUX_MX21_H__ */
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
*/
#ifndef __MACH_IOMUX_V1_H__
#define __MACH_IOMUX_V1_H__
/*
* GPIO Module and I/O Multiplexer
* x = 0..3 for reg_A, reg_B, reg_C, reg_D
*/
#define MXC_DDIR(x) (0x00 + ((x) << 8))
#define MXC_OCR1(x) (0x04 + ((x) << 8))
#define MXC_OCR2(x) (0x08 + ((x) << 8))
#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
#define MXC_DR(x) (0x1c + ((x) << 8))
#define MXC_GIUS(x) (0x20 + ((x) << 8))
#define MXC_SSR(x) (0x24 + ((x) << 8))
#define MXC_ICR1(x) (0x28 + ((x) << 8))
#define MXC_ICR2(x) (0x2c + ((x) << 8))
#define MXC_IMR(x) (0x30 + ((x) << 8))
#define MXC_ISR(x) (0x34 + ((x) << 8))
#define MXC_GPR(x) (0x38 + ((x) << 8))
#define MXC_SWR(x) (0x3c + ((x) << 8))
#define MXC_PUEN(x) (0x40 + ((x) << 8))
#define MX1_NUM_GPIO_PORT 4
#define MX21_NUM_GPIO_PORT 6
#define MX27_NUM_GPIO_PORT 6
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
#define GPIO_OUT (1 << 8)
#define GPIO_IN (0 << 8)
#define GPIO_PUEN (1 << 9)
#define GPIO_PF (1 << 10)
#define GPIO_AF (1 << 11)
#define GPIO_OCR_SHIFT 12
#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
#define GPIO_AOUT_SHIFT 14
#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
#define GPIO_BOUT_SHIFT 16
#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
extern int mxc_gpio_mode(int gpio_mode);
extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label);
extern int imx_iomuxv1_init(void __iomem *base, int numports);
#endif /* __MACH_IOMUX_V1_H__ */
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
* Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
*
* This contains i.MX21-specific hardware definitions. For those
* hardware pieces that are common between i.MX21 and i.MX27, have a
* look at mx2x.h.
*/
#ifndef __MACH_MX21_H__
#define __MACH_MX21_H__
#define MX21_AIPI_BASE_ADDR 0x10000000
#define MX21_AIPI_SIZE SZ_1M
#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
#define MX21_AVIC_BASE_ADDR 0x10040000
#define MX21_SAHB1_BASE_ADDR 0x80000000
#define MX21_SAHB1_SIZE SZ_1M
#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
/* Memory regions and CS */
#define MX21_SDRAM_BASE_ADDR 0xc0000000
#define MX21_CSD1_BASE_ADDR 0xc4000000
#define MX21_CS0_BASE_ADDR 0xc8000000
#define MX21_CS1_BASE_ADDR 0xcc000000
#define MX21_CS2_BASE_ADDR 0xd0000000
#define MX21_CS3_BASE_ADDR 0xd1000000
#define MX21_CS4_BASE_ADDR 0xd2000000
#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
#define MX21_CS5_BASE_ADDR 0xdd000000
/* NAND, SDRAM, WEIM etc controllers */
#define MX21_X_MEMC_BASE_ADDR 0xdf000000
#define MX21_X_MEMC_SIZE SZ_256K
#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
#define MX21_IO_P2V(x) IMX_IO_P2V(x)
#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
/* fixed interrupt numbers */
#include <asm/irq.h>
#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
/* fixed DMA request numbers */
#define MX21_DMA_REQ_CSPI3_RX 1
#define MX21_DMA_REQ_CSPI3_TX 2
#define MX21_DMA_REQ_EXT 3
#define MX21_DMA_REQ_FIRI_RX 4
#define MX21_DMA_REQ_SDHC2 6
#define MX21_DMA_REQ_SDHC1 7
#define MX21_DMA_REQ_SSI2_RX0 8
#define MX21_DMA_REQ_SSI2_TX0 9
#define MX21_DMA_REQ_SSI2_RX1 10
#define MX21_DMA_REQ_SSI2_TX1 11
#define MX21_DMA_REQ_SSI1_RX0 12
#define MX21_DMA_REQ_SSI1_TX0 13
#define MX21_DMA_REQ_SSI1_RX1 14
#define MX21_DMA_REQ_SSI1_TX1 15
#define MX21_DMA_REQ_CSPI2_RX 16
#define MX21_DMA_REQ_CSPI2_TX 17
#define MX21_DMA_REQ_CSPI1_RX 18
#define MX21_DMA_REQ_CSPI1_TX 19
#define MX21_DMA_REQ_UART4_RX 20
#define MX21_DMA_REQ_UART4_TX 21
#define MX21_DMA_REQ_UART3_RX 22
#define MX21_DMA_REQ_UART3_TX 23
#define MX21_DMA_REQ_UART2_RX 24
#define MX21_DMA_REQ_UART2_TX 25
#define MX21_DMA_REQ_UART1_RX 26
#define MX21_DMA_REQ_UART1_TX 27
#define MX21_DMA_REQ_BMI_TX 28
#define MX21_DMA_REQ_BMI_RX 29
#define MX21_DMA_REQ_CSI_STAT 30
#define MX21_DMA_REQ_CSI_RX 31
#endif /* ifndef __MACH_MX21_H__ */
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __MACH_ULPI_H
#define __MACH_ULPI_H
#include <linux/usb/ulpi.h>
#ifdef CONFIG_USB_ULPI_VIEWPORT
static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
{
return otg_ulpi_create(&ulpi_viewport_access_ops, flags);
}
#else
static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
{
return NULL;
}
#endif
#endif /* __MACH_ULPI_H */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment