Commit fa5d5065 authored by Vineet Gupta's avatar Vineet Gupta Committed by Jiri Slaby

ARC: use ASL assembler mnemonic

commit a6416f57 upstream.

ARCompact and ARCv2 only have ASL, while binutils used to support LSL as
a alias mnemonic.

Newer binutils (upstream) don't want to do that so replace it.
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
Signed-off-by: default avatarJiri Slaby <jslaby@suse.cz>
parent db69dff1
...@@ -89,7 +89,7 @@ ex_saved_reg1: ...@@ -89,7 +89,7 @@ ex_saved_reg1:
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
GET_CPU_ID r0 ; get to per cpu scratch mem, GET_CPU_ID r0 ; get to per cpu scratch mem,
lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
add r0, @ex_saved_reg1, r0 add r0, @ex_saved_reg1, r0
#else #else
st r0, [@ex_saved_reg1] st r0, [@ex_saved_reg1]
...@@ -108,7 +108,7 @@ ex_saved_reg1: ...@@ -108,7 +108,7 @@ ex_saved_reg1:
.macro TLBMISS_RESTORE_REGS .macro TLBMISS_RESTORE_REGS
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
GET_CPU_ID r0 ; get to per cpu scratch mem GET_CPU_ID r0 ; get to per cpu scratch mem
lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
add r0, @ex_saved_reg1, r0 add r0, @ex_saved_reg1, r0
ld_s r3, [r0,12] ld_s r3, [r0,12]
ld_s r2, [r0, 8] ld_s r2, [r0, 8]
...@@ -220,7 +220,7 @@ ex_saved_reg1: ...@@ -220,7 +220,7 @@ ex_saved_reg1:
.macro CONV_PTE_TO_TLB .macro CONV_PTE_TO_TLB
and r3, r0, PTE_BITS_RWX ; r w x and r3, r0, PTE_BITS_RWX ; r w x
lsl r2, r3, 3 ; r w x 0 0 0 asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only)
and.f 0, r0, _PAGE_GLOBAL and.f 0, r0, _PAGE_GLOBAL
or.z r2, r2, r3 ; r w x r w x or.z r2, r2, r3 ; r w x r w x
......
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