Commit fa640237 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Stephen Boyd

clk: tegra: pll: Improve PLLM enable-state detection

Power Management Controller (PMC) can override the PLLM clock settings,
including the enable-state. Although PMC could only act as a second level
gate, meaning that PLLM needs to be enabled by the Clock and Reset
Controller (CaR) anyways if we want it to be enabled. Hence, when PLLM is
overridden by PMC, it needs to be enabled by CaR and ungated by PMC in
order to be functional. Please note that this patch doesn't fix any known
problem, and thus, it's merely a minor improvement.

Link: https://lore.kernel.org/linux-arm-kernel/20191210120909.GA2703785@ulmo/T/Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20200709172057.13951-1-digetx@gmail.comReviewed-by: default avatarJon Hunter <jonathanh@nvidia.com>
Tested-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b3a9e3b9
...@@ -327,16 +327,26 @@ int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) ...@@ -327,16 +327,26 @@ int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
return clk_pll_wait_for_lock(pll); return clk_pll_wait_for_lock(pll);
} }
static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
{
u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) &&
!(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE);
}
static int clk_pll_is_enabled(struct clk_hw *hw) static int clk_pll_is_enabled(struct clk_hw *hw)
{ {
struct tegra_clk_pll *pll = to_clk_pll(hw); struct tegra_clk_pll *pll = to_clk_pll(hw);
u32 val; u32 val;
if (pll->params->flags & TEGRA_PLLM) { /*
val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); * Power Management Controller (PMC) can override the PLLM clock
if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) * settings, including the enable-state. The PLLM is enabled when
return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; * PLLM's CaR state is ON and when PLLM isn't gated by PMC.
} */
if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
return 0;
val = pll_readl_base(pll); val = pll_readl_base(pll);
......
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