Commit fbe9c54b authored by Saurav Kashyap's avatar Saurav Kashyap Committed by James Bottomley

[SCSI] qla2xxx: Simplify the ISPFX00 interrupt handler code for ISPFX00.

Signed-off-by: default avatarGiridhar Malavali <giridhar.malavali@qlogic.com>
Signed-off-by: default avatarSaurav Kashyap <saurav.kashyap@qlogic.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 6ac1f3b5
...@@ -3014,6 +3014,7 @@ qlafx00_intr_handler(int irq, void *dev_id) ...@@ -3014,6 +3014,7 @@ qlafx00_intr_handler(int irq, void *dev_id)
struct rsp_que *rsp; struct rsp_que *rsp;
unsigned long flags; unsigned long flags;
uint32_t clr_intr = 0; uint32_t clr_intr = 0;
uint32_t intr_stat = 0;
rsp = (struct rsp_que *) dev_id; rsp = (struct rsp_que *) dev_id;
if (!rsp) { if (!rsp) {
...@@ -3035,34 +3036,26 @@ qlafx00_intr_handler(int irq, void *dev_id) ...@@ -3035,34 +3036,26 @@ qlafx00_intr_handler(int irq, void *dev_id)
stat = QLAFX00_RD_INTR_REG(ha); stat = QLAFX00_RD_INTR_REG(ha);
if (qla2x00_check_reg_for_disconnect(vha, stat)) if (qla2x00_check_reg_for_disconnect(vha, stat))
break; break;
if ((stat & QLAFX00_HST_INT_STS_BITS) == 0) intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
if (!intr_stat)
break; break;
switch (stat & QLAFX00_HST_INT_STS_BITS) { if (stat & QLAFX00_INTR_MB_CMPLT) {
case QLAFX00_INTR_MB_CMPLT:
case QLAFX00_INTR_MB_RSP_CMPLT:
case QLAFX00_INTR_MB_ASYNC_CMPLT:
case QLAFX00_INTR_ALL_CMPLT:
mb[0] = RD_REG_WORD(&reg->mailbox16); mb[0] = RD_REG_WORD(&reg->mailbox16);
qlafx00_mbx_completion(vha, mb[0]); qlafx00_mbx_completion(vha, mb[0]);
status |= MBX_INTERRUPT; status |= MBX_INTERRUPT;
clr_intr |= QLAFX00_INTR_MB_CMPLT; clr_intr |= QLAFX00_INTR_MB_CMPLT;
break; }
case QLAFX00_INTR_ASYNC_CMPLT: if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
case QLAFX00_INTR_RSP_ASYNC_CMPLT:
ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0); ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
qlafx00_async_event(vha); qlafx00_async_event(vha);
clr_intr |= QLAFX00_INTR_ASYNC_CMPLT; clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
break; }
case QLAFX00_INTR_RSP_CMPLT: if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
qlafx00_process_response_queue(vha, rsp); qlafx00_process_response_queue(vha, rsp);
clr_intr |= QLAFX00_INTR_RSP_CMPLT; clr_intr |= QLAFX00_INTR_RSP_CMPLT;
break;
default:
ql_dbg(ql_dbg_async, vha, 0x507a,
"Unrecognized interrupt type (%d).\n", stat);
break;
} }
QLAFX00_CLR_INTR_REG(ha, clr_intr); QLAFX00_CLR_INTR_REG(ha, clr_intr);
QLAFX00_RD_INTR_REG(ha); QLAFX00_RD_INTR_REG(ha);
} }
......
...@@ -336,11 +336,7 @@ struct config_info_data { ...@@ -336,11 +336,7 @@ struct config_info_data {
#define QLAFX00_INTR_MB_CMPLT 0x1 #define QLAFX00_INTR_MB_CMPLT 0x1
#define QLAFX00_INTR_RSP_CMPLT 0x2 #define QLAFX00_INTR_RSP_CMPLT 0x2
#define QLAFX00_INTR_MB_RSP_CMPLT 0x3
#define QLAFX00_INTR_ASYNC_CMPLT 0x4 #define QLAFX00_INTR_ASYNC_CMPLT 0x4
#define QLAFX00_INTR_MB_ASYNC_CMPLT 0x5
#define QLAFX00_INTR_RSP_ASYNC_CMPLT 0x6
#define QLAFX00_INTR_ALL_CMPLT 0x7
#define QLAFX00_MBA_SYSTEM_ERR 0x8002 #define QLAFX00_MBA_SYSTEM_ERR 0x8002
#define QLAFX00_MBA_TEMP_OVER 0x8005 #define QLAFX00_MBA_TEMP_OVER 0x8005
......
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