Commit fc838c77 authored by Shahar S Matityahu's avatar Shahar S Matityahu Committed by Luca Coelho

iwlwifi: dbg: fix debug monitor stop and restart delays

The driver should delay only in recording stop flow between writing to
DBGC_IN_SAMPLE register and DBGC_OUT_CTRL register. Any other delay is
not needed.

Change the following:
1. Remove any unnecessary delays in the flow
2. Increase the delay in the stop recording flow since 100 micro is
   not enough
3. Use usleep_range instead of delay since the driver is allowed to
   sleep in this flow.
Signed-off-by: default avatarShahar S Matityahu <shahar.s.matityahu@intel.com>
Fixes: 5cfe79c8 ("iwlwifi: fw: stop and start debugging using host command")
Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent c4d3f2ee
...@@ -2386,8 +2386,6 @@ static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) ...@@ -2386,8 +2386,6 @@ static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx)
/* start recording again if the firmware is not crashed */ /* start recording again if the firmware is not crashed */
if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) && if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) &&
fwrt->fw->dbg.dest_tlv) { fwrt->fw->dbg.dest_tlv) {
/* wait before we collect the data till the DBGC stop */
udelay(500);
iwl_fw_dbg_restart_recording(fwrt, &params); iwl_fw_dbg_restart_recording(fwrt, &params);
} }
......
...@@ -295,7 +295,10 @@ _iwl_fw_dbg_stop_recording(struct iwl_trans *trans, ...@@ -295,7 +295,10 @@ _iwl_fw_dbg_stop_recording(struct iwl_trans *trans,
} }
iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
udelay(100); /* wait for the DBGC to finish writing the internal buffer to DRAM to
* avoid halting the HW while writing
*/
usleep_range(700, 1000);
iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
#ifdef CONFIG_IWLWIFI_DEBUGFS #ifdef CONFIG_IWLWIFI_DEBUGFS
trans->dbg_rec_on = false; trans->dbg_rec_on = false;
...@@ -325,7 +328,6 @@ _iwl_fw_dbg_restart_recording(struct iwl_trans *trans, ...@@ -325,7 +328,6 @@ _iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
} else { } else {
iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
udelay(100);
iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
} }
} }
......
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