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Commit fd166a18 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/disp: cosmetic changes 

This is purely preparation for upcoming commits, there should be no
code changes here.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent e2f1cf25
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Showing with 826 additions and 833 deletions
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
View file @ fd166a18
......@@ -4,7 +4,7 @@
#include <core/event.h>
struct nvkm_disp {
struct nvkm_engine base;
struct nvkm_engine engine;
struct list_head outp;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
View file @ fd166a18
......@@ -127,7 +127,7 @@ _nvkm_disp_fini(struct nvkm_object *object, bool suspend)
goto fail_outp;
}
return nvkm_engine_fini(&disp->base, suspend);
return nvkm_engine_fini(&disp->engine, suspend);
fail_outp:
list_for_each_entry_continue_reverse(outp, &disp->outp, head) {
......@@ -144,7 +144,7 @@ _nvkm_disp_init(struct nvkm_object *object)
struct nvkm_output *outp;
int ret;
ret = nvkm_engine_init(&disp->base);
ret = nvkm_engine_init(&disp->engine);
if (ret)
return ret;
......@@ -179,7 +179,7 @@ _nvkm_disp_dtor(struct nvkm_object *object)
}
}
nvkm_engine_destroy(&disp->base);
nvkm_engine_destroy(&disp->engine);
}
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
View file @ fd166a18
......@@ -53,9 +53,9 @@ nv50_dac_power(NV50_DISP_MTHD_V1)
} else
return ret;
nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
nv_mask(priv, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);
nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);
nv_mask(disp, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);
nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);
return 0;
}
......@@ -79,18 +79,18 @@ nv50_dac_sense(NV50_DISP_MTHD_V1)
} else
return ret;
nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);
nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80150000);
nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);
nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
nv_wr32(disp, 0x61a00c + doff, 0x00100000 | loadval);
mdelay(9);
udelay(500);
loadval = nv_mask(priv, 0x61a00c + doff, 0xffffffff, 0x00000000);
loadval = nv_mask(disp, 0x61a00c + doff, 0xffffffff, 0x00000000);
nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);
nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80550000);
nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);
nv_debug(priv, "DAC%d sense: 0x%08x\n", outp->or, loadval);
nv_debug(disp, "DAC%d sense: 0x%08x\n", outp->or, loadval);
if (!(loadval & 0x80000000))
return -ETIMEDOUT;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
View file @ fd166a18
......@@ -322,7 +322,7 @@ void
nvkm_dp_train(struct work_struct *w)
{
struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
const struct dp_rates *cfg = nvkm_dp_rates;
struct dp_state _dp = {
.outp = outp,
......@@ -330,11 +330,11 @@ nvkm_dp_train(struct work_struct *w)
u32 datarate = 0;
int ret;
if (!outp->base.info.location && priv->sor.magic)
priv->sor.magic(&outp->base);
if (!outp->base.info.location && disp->sor.magic)
disp->sor.magic(&outp->base);
/* bring capabilities within encoder limits */
if (nv_mclass(priv) < GF110_DISP)
if (nv_mclass(disp) < GF110_DISP)
outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;
if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) {
outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
View file @ fd166a18
......@@ -223,33 +223,33 @@ g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
struct nv50_disp *disp;
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
"display", &priv);
*pobject = nv_object(priv);
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = g84_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
priv->sclass = g84_disp_sclass;
priv->head.nr = 2;
priv->dac.nr = 3;
priv->sor.nr = 2;
priv->pior.nr = 3;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.hdmi = g84_hdmi_ctrl;
priv->pior.power = nv50_pior_power;
nv_engine(disp)->sclass = g84_disp_main_oclass;
nv_engine(disp)->cclass = &nv50_disp_cclass;
nv_subdev(disp)->intr = nv50_disp_intr;
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
disp->sclass = g84_disp_sclass;
disp->head.nr = 2;
disp->dac.nr = 3;
disp->sor.nr = 2;
disp->pior.nr = 3;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hdmi = g84_hdmi_ctrl;
disp->pior.power = nv50_pior_power;
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
View file @ fd166a18
......@@ -83,33 +83,33 @@ g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
struct nv50_disp *disp;
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
"display", &priv);
*pobject = nv_object(priv);
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = g94_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
priv->sclass = g94_disp_sclass;
priv->head.nr = 2;
priv->dac.nr = 3;
priv->sor.nr = 4;
priv->pior.nr = 3;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.hdmi = g84_hdmi_ctrl;
priv->pior.power = nv50_pior_power;
nv_engine(disp)->sclass = g94_disp_main_oclass;
nv_engine(disp)->cclass = &nv50_disp_cclass;
nv_subdev(disp)->intr = nv50_disp_intr;
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
disp->sclass = g94_disp_sclass;
disp->head.nr = 2;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->pior.nr = 3;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hdmi = g84_hdmi_ctrl;
disp->pior.power = nv50_pior_power;
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
View file @ fd166a18
......@@ -219,33 +219,33 @@ gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
struct nv50_disp *disp;
int heads = nv_rd32(parent, 0x022448);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &priv);
*pobject = nv_object(priv);
"PDISP", "display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = gk104_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = gf110_disp_intr;
INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
priv->sclass = gk104_disp_sclass;
priv->head.nr = heads;
priv->dac.nr = 3;
priv->sor.nr = 4;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.hda_eld = gf110_hda_eld;
priv->sor.hdmi = gk104_hdmi_ctrl;
nv_engine(disp)->sclass = gk104_disp_main_oclass;
nv_engine(disp)->cclass = &nv50_disp_cclass;
nv_subdev(disp)->intr = gf110_disp_intr;
INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor);
disp->sclass = gk104_disp_sclass;
disp->head.nr = heads;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gf110_hda_eld;
disp->sor.hdmi = gk104_hdmi_ctrl;
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
View file @ fd166a18
......@@ -54,33 +54,33 @@ gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
struct nv50_disp *disp;
int heads = nv_rd32(parent, 0x022448);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &priv);
*pobject = nv_object(priv);
"PDISP", "display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = gk110_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = gf110_disp_intr;
INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
priv->sclass = gk110_disp_sclass;
priv->head.nr = heads;
priv->dac.nr = 3;
priv->sor.nr = 4;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.hda_eld = gf110_hda_eld;
priv->sor.hdmi = gk104_hdmi_ctrl;
nv_engine(disp)->sclass = gk110_disp_main_oclass;
nv_engine(disp)->cclass = &nv50_disp_cclass;
nv_subdev(disp)->intr = gf110_disp_intr;
INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor);
disp->sclass = gk110_disp_sclass;
disp->head.nr = heads;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gf110_hda_eld;
disp->sor.hdmi = gk104_hdmi_ctrl;
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
View file @ fd166a18
......@@ -54,33 +54,33 @@ gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
struct nv50_disp *disp;
int heads = nv_rd32(parent, 0x022448);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &priv);
*pobject = nv_object(priv);
"PDISP", "display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = gm107_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = gf110_disp_intr;
INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
priv->sclass = gm107_disp_sclass;
priv->head.nr = heads;
priv->dac.nr = 3;
priv->sor.nr = 4;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.hda_eld = gf110_hda_eld;
priv->sor.hdmi = gk104_hdmi_ctrl;
nv_engine(disp)->sclass = gm107_disp_main_oclass;
nv_engine(disp)->cclass = &nv50_disp_cclass;
nv_subdev(disp)->intr = gf110_disp_intr;
INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor);
disp->sclass = gm107_disp_sclass;
disp->head.nr = heads;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gf110_hda_eld;
disp->sor.hdmi = gk104_hdmi_ctrl;
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
View file @ fd166a18
......@@ -55,34 +55,34 @@ gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
struct nv50_disp *disp;
int heads = nv_rd32(parent, 0x022448);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &priv);
*pobject = nv_object(priv);
"PDISP", "display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = gm204_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = gf110_disp_intr;
INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
priv->sclass = gm204_disp_sclass;
priv->head.nr = heads;
priv->dac.nr = 3;
priv->sor.nr = 4;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.hda_eld = gf110_hda_eld;
priv->sor.hdmi = gf110_hdmi_ctrl;
priv->sor.magic = gm204_sor_magic;
nv_engine(disp)->sclass = gm204_disp_main_oclass;
nv_engine(disp)->cclass = &nv50_disp_cclass;
nv_subdev(disp)->intr = gf110_disp_intr;
INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor);
disp->sclass = gm204_disp_sclass;
disp->head.nr = heads;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gf110_hda_eld;
disp->sor.hdmi = gf110_hdmi_ctrl;
disp->sor.magic = gm204_sor_magic;
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
View file @ fd166a18
......@@ -99,33 +99,33 @@ gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
struct nv50_disp *disp;
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
"display", &priv);
*pobject = nv_object(priv);
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = gt200_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
priv->sclass = gt200_disp_sclass;
priv->head.nr = 2;
priv->dac.nr = 3;
priv->sor.nr = 2;
priv->pior.nr = 3;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.hdmi = g84_hdmi_ctrl;
priv->pior.power = nv50_pior_power;
nv_engine(disp)->sclass = gt200_disp_main_oclass;
nv_engine(disp)->cclass = &nv50_disp_cclass;
nv_subdev(disp)->intr = nv50_disp_intr;
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
disp->sclass = gt200_disp_sclass;
disp->head.nr = 2;
disp->dac.nr = 3;
disp->sor.nr = 2;
disp->pior.nr = 3;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hdmi = g84_hdmi_ctrl;
disp->pior.power = nv50_pior_power;
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
View file @ fd166a18
......@@ -54,34 +54,34 @@ gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
struct nv50_disp *disp;
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
"display", &priv);
*pobject = nv_object(priv);
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = gt215_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
priv->sclass = gt215_disp_sclass;
priv->head.nr = 2;
priv->dac.nr = 3;
priv->sor.nr = 4;
priv->pior.nr = 3;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.hda_eld = gt215_hda_eld;
priv->sor.hdmi = gt215_hdmi_ctrl;
priv->pior.power = nv50_pior_power;
nv_engine(disp)->sclass = gt215_disp_main_oclass;
nv_engine(disp)->cclass = &nv50_disp_cclass;
nv_subdev(disp)->intr = nv50_disp_intr;
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
disp->sclass = gt215_disp_sclass;
disp->head.nr = 2;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->pior.nr = 3;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gt215_hda_eld;
disp->sor.hdmi = gt215_hdmi_ctrl;
disp->pior.power = nv50_pior_power;
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c
View file @ fd166a18
......@@ -52,21 +52,21 @@ gf110_hda_eld(NV50_DISP_MTHD_V1)
if (size && args->v0.data[0]) {
if (outp->info.type == DCB_OUTPUT_DP) {
nv_mask(priv, 0x616618 + hoff, 0x8000000c, 0x80000001);
nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000);
nv_mask(disp, 0x616618 + hoff, 0x8000000c, 0x80000001);
nv_wait(disp, 0x616618 + hoff, 0x80000000, 0x00000000);
}
nv_mask(priv, 0x616548 + hoff, 0x00000070, 0x00000000);
nv_mask(disp, 0x616548 + hoff, 0x00000070, 0x00000000);
for (i = 0; i < size; i++)
nv_wr32(priv, 0x10ec00 + soff, (i << 8) | args->v0.data[i]);
nv_wr32(disp, 0x10ec00 + soff, (i << 8) | args->v0.data[i]);
for (; i < 0x60; i++)
nv_wr32(priv, 0x10ec00 + soff, (i << 8));
nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000003);
nv_wr32(disp, 0x10ec00 + soff, (i << 8));
nv_mask(disp, 0x10ec10 + soff, 0x80000003, 0x80000003);
} else {
if (outp->info.type == DCB_OUTPUT_DP) {
nv_mask(priv, 0x616618 + hoff, 0x80000001, 0x80000000);
nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000);
nv_mask(disp, 0x616618 + hoff, 0x80000001, 0x80000000);
nv_wait(disp, 0x616618 + hoff, 0x80000000, 0x00000000);
}
nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size);
nv_mask(disp, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size);
}
return 0;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c
View file @ fd166a18
......@@ -49,20 +49,20 @@ gt215_hda_eld(NV50_DISP_MTHD_V1)
if (size && args->v0.data[0]) {
if (outp->info.type == DCB_OUTPUT_DP) {
nv_mask(priv, 0x61c1e0 + soff, 0x8000000d, 0x80000001);
nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000);
nv_mask(disp, 0x61c1e0 + soff, 0x8000000d, 0x80000001);
nv_wait(disp, 0x61c1e0 + soff, 0x80000000, 0x00000000);
}
for (i = 0; i < size; i++)
nv_wr32(priv, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
nv_wr32(disp, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
for (; i < 0x60; i++)
nv_wr32(priv, 0x61c440 + soff, (i << 8));
nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000003);
nv_wr32(disp, 0x61c440 + soff, (i << 8));
nv_mask(disp, 0x61c448 + soff, 0x80000003, 0x80000003);
} else {
if (outp->info.type == DCB_OUTPUT_DP) {
nv_mask(priv, 0x61c1e0 + soff, 0x80000001, 0x80000000);
nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000);
nv_mask(disp, 0x61c1e0 + soff, 0x80000001, 0x80000000);
nv_wait(disp, 0x61c1e0 + soff, 0x80000000, 0x00000000);
}
nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size);
nv_mask(disp, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size);
}
return 0;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c
View file @ fd166a18
......@@ -54,38 +54,38 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
return ret;
if (!(ctrl & 0x40000000)) {
nv_mask(priv, 0x6165a4 + hoff, 0x40000000, 0x00000000);
nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
nv_mask(disp, 0x6165a4 + hoff, 0x40000000, 0x00000000);
nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000000);
nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000000);
return 0;
}
/* AVI InfoFrame */
nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
nv_wr32(priv, 0x616528 + hoff, 0x000d0282);
nv_wr32(priv, 0x61652c + hoff, 0x0000006f);
nv_wr32(priv, 0x616530 + hoff, 0x00000000);
nv_wr32(priv, 0x616534 + hoff, 0x00000000);
nv_wr32(priv, 0x616538 + hoff, 0x00000000);
nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000001);
nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000000);
nv_wr32(disp, 0x616528 + hoff, 0x000d0282);
nv_wr32(disp, 0x61652c + hoff, 0x0000006f);
nv_wr32(disp, 0x616530 + hoff, 0x00000000);
nv_wr32(disp, 0x616534 + hoff, 0x00000000);
nv_wr32(disp, 0x616538 + hoff, 0x00000000);
nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000001);
/* Audio InfoFrame */
nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
nv_wr32(priv, 0x616508 + hoff, 0x000a0184);
nv_wr32(priv, 0x61650c + hoff, 0x00000071);
nv_wr32(priv, 0x616510 + hoff, 0x00000000);
nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001);
nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000000);
nv_wr32(disp, 0x616508 + hoff, 0x000a0184);
nv_wr32(disp, 0x61650c + hoff, 0x00000071);
nv_wr32(disp, 0x616510 + hoff, 0x00000000);
nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000001);
nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
nv_mask(disp, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
nv_mask(disp, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
nv_mask(disp, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
/* ??? */
nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
nv_mask(disp, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
nv_mask(disp, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
nv_mask(disp, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
/* HDMI_CTRL */
nv_mask(priv, 0x6165a4 + hoff, 0x5f1f007f, ctrl);
nv_mask(disp, 0x6165a4 + hoff, 0x5f1f007f, ctrl);
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c
View file @ fd166a18
......@@ -53,27 +53,27 @@ gf110_hdmi_ctrl(NV50_DISP_MTHD_V1)
return ret;
if (!(ctrl & 0x40000000)) {
nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000);
nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000);
nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000);
nv_mask(disp, 0x616798 + hoff, 0x40000000, 0x00000000);
nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000000);
nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000000);
return 0;
}
/* AVI InfoFrame */
nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000);
nv_wr32(priv, 0x61671c + hoff, 0x000d0282);
nv_wr32(priv, 0x616720 + hoff, 0x0000006f);
nv_wr32(priv, 0x616724 + hoff, 0x00000000);
nv_wr32(priv, 0x616728 + hoff, 0x00000000);
nv_wr32(priv, 0x61672c + hoff, 0x00000000);
nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000001);
nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000000);
nv_wr32(disp, 0x61671c + hoff, 0x000d0282);
nv_wr32(disp, 0x616720 + hoff, 0x0000006f);
nv_wr32(disp, 0x616724 + hoff, 0x00000000);
nv_wr32(disp, 0x616728 + hoff, 0x00000000);
nv_wr32(disp, 0x61672c + hoff, 0x00000000);
nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000001);
/* ??? InfoFrame? */
nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000);
nv_wr32(priv, 0x6167ac + hoff, 0x00000010);
nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000001);
nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000000);
nv_wr32(disp, 0x6167ac + hoff, 0x00000010);
nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000001);
/* HDMI_CTRL */
nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl);
nv_mask(disp, 0x616798 + hoff, 0x401f007f, ctrl);
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c
View file @ fd166a18
......@@ -54,30 +54,30 @@ gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
return ret;
if (!(ctrl & 0x40000000)) {
nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000);
nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000);
nv_mask(disp, 0x616798 + hoff, 0x40000000, 0x00000000);
nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000000);
return 0;
}
/* AVI InfoFrame */
nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000);
nv_wr32(priv, 0x690008 + hdmi, 0x000d0282);
nv_wr32(priv, 0x69000c + hdmi, 0x0000006f);
nv_wr32(priv, 0x690010 + hdmi, 0x00000000);
nv_wr32(priv, 0x690014 + hdmi, 0x00000000);
nv_wr32(priv, 0x690018 + hdmi, 0x00000000);
nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000001);
nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000000);
nv_wr32(disp, 0x690008 + hdmi, 0x000d0282);
nv_wr32(disp, 0x69000c + hdmi, 0x0000006f);
nv_wr32(disp, 0x690010 + hdmi, 0x00000000);
nv_wr32(disp, 0x690014 + hdmi, 0x00000000);
nv_wr32(disp, 0x690018 + hdmi, 0x00000000);
nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000001);
/* ??? InfoFrame? */
nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
nv_wr32(priv, 0x6900cc + hdmi, 0x00000010);
nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000001);
nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
nv_wr32(disp, 0x6900cc + hdmi, 0x00000010);
nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000001);
/* ??? */
nv_wr32(priv, 0x690080 + hdmi, 0x82000000);
nv_wr32(disp, 0x690080 + hdmi, 0x82000000);
/* HDMI_CTRL */
nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl);
nv_mask(disp, 0x616798 + hoff, 0x401f007f, ctrl);
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c
View file @ fd166a18
......@@ -55,38 +55,38 @@ gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
return ret;
if (!(ctrl & 0x40000000)) {
nv_mask(priv, 0x61c5a4 + soff, 0x40000000, 0x00000000);
nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000);
nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000);
nv_mask(disp, 0x61c5a4 + soff, 0x40000000, 0x00000000);
nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000000);
nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000000);
return 0;
}
/* AVI InfoFrame */
nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000);
nv_wr32(priv, 0x61c528 + soff, 0x000d0282);
nv_wr32(priv, 0x61c52c + soff, 0x0000006f);
nv_wr32(priv, 0x61c530 + soff, 0x00000000);
nv_wr32(priv, 0x61c534 + soff, 0x00000000);
nv_wr32(priv, 0x61c538 + soff, 0x00000000);
nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000001);
nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000000);
nv_wr32(disp, 0x61c528 + soff, 0x000d0282);
nv_wr32(disp, 0x61c52c + soff, 0x0000006f);
nv_wr32(disp, 0x61c530 + soff, 0x00000000);
nv_wr32(disp, 0x61c534 + soff, 0x00000000);
nv_wr32(disp, 0x61c538 + soff, 0x00000000);
nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000001);
/* Audio InfoFrame */
nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000);
nv_wr32(priv, 0x61c508 + soff, 0x000a0184);
nv_wr32(priv, 0x61c50c + soff, 0x00000071);
nv_wr32(priv, 0x61c510 + soff, 0x00000000);
nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001);
nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000000);
nv_wr32(disp, 0x61c508 + soff, 0x000a0184);
nv_wr32(disp, 0x61c50c + soff, 0x00000071);
nv_wr32(disp, 0x61c510 + soff, 0x00000000);
nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000001);
nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
nv_mask(priv, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
nv_mask(disp, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
nv_mask(disp, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
nv_mask(disp, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
/* ??? */
nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
nv_mask(disp, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
nv_mask(disp, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
nv_mask(disp, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
/* HDMI_CTRL */
nv_mask(priv, 0x61c5a4 + soff, 0x5f1f007f, ctrl);
nv_mask(disp, 0x61c5a4 + soff, 0x5f1f007f, ctrl);
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
View file @ fd166a18
......@@ -28,12 +28,8 @@
#include <nvif/class.h>
#include <nvif/unpack.h>
struct nv04_disp_priv {
struct nvkm_disp base;
};
static int
nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv,
nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp,
void *data, u32 size, int head)
{
const u32 hoff = head * 0x2000;
......@@ -46,12 +42,12 @@ nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv,
nv_ioctl(object, "disp scanoutpos size %d\n", size);
if (nvif_unpack(args->v0, 0, 0, false)) {
nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version);
args->v0.vblanks = nv_rd32(priv, 0x680800 + hoff) & 0xffff;
args->v0.vtotal = nv_rd32(priv, 0x680804 + hoff) & 0xffff;
args->v0.vblanks = nv_rd32(disp, 0x680800 + hoff) & 0xffff;
args->v0.vtotal = nv_rd32(disp, 0x680804 + hoff) & 0xffff;
args->v0.vblanke = args->v0.vtotal - 1;
args->v0.hblanks = nv_rd32(priv, 0x680820 + hoff) & 0xffff;
args->v0.htotal = nv_rd32(priv, 0x680824 + hoff) & 0xffff;
args->v0.hblanks = nv_rd32(disp, 0x680820 + hoff) & 0xffff;
args->v0.htotal = nv_rd32(disp, 0x680824 + hoff) & 0xffff;
args->v0.hblanke = args->v0.htotal - 1;
/*
......@@ -63,7 +59,7 @@ nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv,
return -ENOTSUPP;
args->v0.time[0] = ktime_to_ns(ktime_get());
line = nv_rd32(priv, 0x600868 + hoff);
line = nv_rd32(disp, 0x600868 + hoff);
args->v0.time[1] = ktime_to_ns(ktime_get());
args->v0.hline = (line & 0xffff0000) >> 16;
args->v0.vline = (line & 0x0000ffff);
......@@ -79,7 +75,7 @@ nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
union {
struct nv04_disp_mthd_v0 v0;
} *args = data;
struct nv04_disp_priv *priv = (void *)object->engine;
struct nvkm_disp *disp = (void *)object->engine;
int head, ret;
nv_ioctl(object, "disp mthd size %d\n", size);
......@@ -96,7 +92,7 @@ nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
switch (mthd) {
case NV04_DISP_SCANOUTPOS:
return nv04_disp_scanoutpos(object, priv, data, size, head);
return nv04_disp_scanoutpos(object, disp, data, size, head);
default:
break;
}
......@@ -148,27 +144,27 @@ nv04_disp_vblank_func = {
static void
nv04_disp_intr(struct nvkm_subdev *subdev)
{
struct nv04_disp_priv *priv = (void *)subdev;
u32 crtc0 = nv_rd32(priv, 0x600100);
u32 crtc1 = nv_rd32(priv, 0x602100);
struct nvkm_disp *disp = (void *)subdev;
u32 crtc0 = nv_rd32(disp, 0x600100);
u32 crtc1 = nv_rd32(disp, 0x602100);
u32 pvideo;
if (crtc0 & 0x00000001) {
nvkm_disp_vblank(&priv->base, 0);
nv_wr32(priv, 0x600100, 0x00000001);
nvkm_disp_vblank(disp, 0);
nv_wr32(disp, 0x600100, 0x00000001);
}
if (crtc1 & 0x00000001) {
nvkm_disp_vblank(&priv->base, 1);
nv_wr32(priv, 0x602100, 0x00000001);
nvkm_disp_vblank(disp, 1);
nv_wr32(disp, 0x602100, 0x00000001);
}
if (nv_device(priv)->chipset >= 0x10 &&
nv_device(priv)->chipset <= 0x40) {
pvideo = nv_rd32(priv, 0x8100);
if (nv_device(disp)->chipset >= 0x10 &&
nv_device(disp)->chipset <= 0x40) {
pvideo = nv_rd32(disp, 0x8100);
if (pvideo & ~0x11)
nv_info(priv, "PVIDEO intr: %08x\n", pvideo);
nv_wr32(priv, 0x8100, pvideo);
nv_info(disp, "PVIDEO intr: %08x\n", pvideo);
nv_wr32(disp, 0x8100, pvideo);
}
}
......@@ -177,17 +173,17 @@ nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv04_disp_priv *priv;
struct nvkm_disp *disp;
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY",
"display", &priv);
*pobject = nv_object(priv);
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
nv_engine(priv)->sclass = nv04_disp_sclass;
nv_subdev(priv)->intr = nv04_disp_intr;
nv_engine(disp)->sclass = nv04_disp_sclass;
nv_subdev(disp)->intr = nv04_disp_intr;
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
View file @ fd166a18
......@@ -5,11 +5,11 @@ struct nvkm_output;
struct nvkm_output_dp;
#define NV50_DISP_MTHD_ struct nvkm_object *object, \
struct nv50_disp_priv *priv, void *data, u32 size
struct nv50_disp *disp, void *data, u32 size
#define NV50_DISP_MTHD_V0 NV50_DISP_MTHD_, int head
#define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp
struct nv50_disp_priv {
struct nv50_disp {
struct nvkm_disp base;
struct nvkm_oclass *sclass;
......@@ -102,7 +102,7 @@ void nv50_disp_chan_wr32(struct nvkm_object *, u64, u32);
extern const struct nvkm_event_func nv50_disp_chan_uevent;
int nv50_disp_chan_uevent_ctor(struct nvkm_object *, void *, u32,
struct nvkm_notify *);
void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int);
void nv50_disp_chan_uevent_send(struct nv50_disp *, int);
extern const struct nvkm_event_func gf110_disp_chan_uevent;
......@@ -177,7 +177,7 @@ int nv50_disp_main_ctor(struct nvkm_object *, struct nvkm_object *,
void nv50_disp_main_dtor(struct nvkm_object *);
extern struct nvkm_omthds nv50_disp_main_omthds[];
extern struct nvkm_oclass nv50_disp_cclass;
void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,
void nv50_disp_mthd_chan(struct nv50_disp *, int debug, int head,
const struct nv50_disp_mthd_chan *);
void nv50_disp_intr_supervisor(struct work_struct *);
void nv50_disp_intr(struct nvkm_subdev *);
......@@ -214,7 +214,7 @@ extern struct nvkm_output_dp_impl nv50_pior_dp_impl;
extern struct nvkm_oclass *nv50_disp_outp_sclass[];
extern struct nvkm_output_dp_impl g94_sor_dp_impl;
u32 g94_sor_dp_lane_map(struct nv50_disp_priv *, u8 lane);
u32 g94_sor_dp_lane_map(struct nv50_disp *, u8 lane);
int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
extern struct nvkm_oclass *g94_disp_outp_sclass[];
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
View file @ fd166a18
......@@ -162,9 +162,9 @@ nv50_pior_power(NV50_DISP_MTHD_V1)
} else
return ret;
nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000);
nv_mask(priv, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl);
nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000);
priv->pior.type[outp->or] = type;
nv_wait(disp, 0x61e004 + soff, 0x80000000, 0x00000000);
nv_mask(disp, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl);
nv_wait(disp, 0x61e004 + soff, 0x80000000, 0x00000000);
disp->pior.type[outp->or] = type;
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
View file @ fd166a18
......@@ -39,14 +39,14 @@ g94_sor_loff(struct nvkm_output_dp *outp)
}
u32
g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
g94_sor_dp_lane_map(struct nv50_disp *disp, u8 lane)
{
static const u8 gm100[] = { 0, 8, 16, 24 };
static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
static const u8 g94[] = { 16, 8, 0, 24 };
if (nv_device(priv)->chipset >= 0x110)
if (nv_device(disp)->chipset >= 0x110)
return gm100[lane];
if (nv_device(priv)->chipset == 0xaf)
if (nv_device(disp)->chipset == 0xaf)
return mcp89[lane];
return g94[lane];
}
......@@ -54,33 +54,33 @@ g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
static int
g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
const u32 loff = g94_sor_loff(outp);
nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24);
nv_mask(disp, 0x61c10c + loff, 0x0f000000, pattern << 24);
return 0;
}
int
g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
const u32 soff = g94_sor_soff(outp);
const u32 loff = g94_sor_loff(outp);
u32 mask = 0, i;
for (i = 0; i < nr; i++)
mask |= 1 << (g94_sor_dp_lane_map(priv, i) >> 3);
mask |= 1 << (g94_sor_dp_lane_map(disp, i) >> 3);
nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask);
nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000);
nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000);
nv_mask(disp, 0x61c130 + loff, 0x0000000f, mask);
nv_mask(disp, 0x61c034 + soff, 0x80000000, 0x80000000);
nv_wait(disp, 0x61c034 + soff, 0x80000000, 0x00000000);
return 0;
}
static int
g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
const u32 soff = g94_sor_soff(outp);
const u32 loff = g94_sor_loff(outp);
u32 dpctrl = 0x00000000;
......@@ -92,17 +92,17 @@ g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
if (bw > 0x06)
clksor |= 0x00040000;
nv_mask(priv, 0x614300 + soff, 0x000c0000, clksor);
nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl);
nv_mask(disp, 0x614300 + soff, 0x000c0000, clksor);
nv_mask(disp, 0x61c10c + loff, 0x001f4000, dpctrl);
return 0;
}
static int
g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nvkm_bios *bios = nvkm_bios(priv);
const u32 shift = g94_sor_dp_lane_map(priv, ln);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
struct nvkm_bios *bios = nvkm_bios(disp);
const u32 shift = g94_sor_dp_lane_map(disp, ln);
const u32 loff = g94_sor_loff(outp);
u32 addr, data[3];
u8 ver, hdr, cnt, len;
......@@ -120,14 +120,14 @@ g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
if (!addr)
return -EINVAL;
data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(priv, 0x61c130 + loff);
data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(disp, 0x61c130 + loff);
if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
nv_wr32(priv, 0x61c130 + loff, data[2]);
nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
nv_wr32(disp, 0x61c130 + loff, data[2]);
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c
View file @ fd166a18
......@@ -39,16 +39,16 @@ gf110_sor_loff(struct nvkm_output_dp *outp)
static int
gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
const u32 loff = gf110_sor_loff(outp);
nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
nv_mask(disp, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
return 0;
}
int
gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
const u32 soff = gf110_sor_soff(outp);
const u32 loff = gf110_sor_loff(outp);
u32 dpctrl = 0x00000000;
......@@ -59,8 +59,8 @@ gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
if (ef)
dpctrl |= 0x00004000;
nv_mask(priv, 0x612300 + soff, 0x007c0000, clksor);
nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl);
nv_mask(disp, 0x612300 + soff, 0x007c0000, clksor);
nv_mask(disp, 0x61c10c + loff, 0x001f4000, dpctrl);
return 0;
}
......@@ -68,9 +68,9 @@ static int
gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
int ln, int vs, int pe, int pc)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nvkm_bios *bios = nvkm_bios(priv);
const u32 shift = g94_sor_dp_lane_map(priv, ln);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
struct nvkm_bios *bios = nvkm_bios(disp);
const u32 shift = g94_sor_dp_lane_map(disp, ln);
const u32 loff = gf110_sor_loff(outp);
u32 addr, data[4];
u8 ver, hdr, cnt, len;
......@@ -88,16 +88,16 @@ gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
if (!addr)
return -EINVAL;
data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(priv, 0x61c130 + loff);
data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(disp, 0x61c130 + loff);
if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
nv_wr32(priv, 0x61c130 + loff, data[2]);
data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift);
nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
nv_wr32(disp, 0x61c130 + loff, data[2]);
data[3] = nv_rd32(disp, 0x61c13c + loff) & ~(0x000000ff << shift);
nv_wr32(disp, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
View file @ fd166a18
......@@ -41,17 +41,17 @@ gm204_sor_loff(struct nvkm_output_dp *outp)
void
gm204_sor_magic(struct nvkm_output *outp)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
const u32 soff = outp->or * 0x100;
const u32 data = outp->or + 1;
if (outp->info.sorconf.link & 1)
nv_mask(priv, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
nv_mask(disp, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
if (outp->info.sorconf.link & 2)
nv_mask(priv, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
nv_mask(disp, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
}
static inline u32
gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
gm204_sor_dp_lane_map(struct nv50_disp *disp, u8 lane)
{
return lane * 0x08;
}
......@@ -59,30 +59,30 @@ gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
static int
gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
const u32 soff = gm204_sor_soff(outp);
const u32 data = 0x01010101 * pattern;
if (outp->base.info.sorconf.link & 1)
nv_mask(priv, 0x61c110 + soff, 0x0f0f0f0f, data);
nv_mask(disp, 0x61c110 + soff, 0x0f0f0f0f, data);
else
nv_mask(priv, 0x61c12c + soff, 0x0f0f0f0f, data);
nv_mask(disp, 0x61c12c + soff, 0x0f0f0f0f, data);
return 0;
}
static int
gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
const u32 soff = gm204_sor_soff(outp);
const u32 loff = gm204_sor_loff(outp);
u32 mask = 0, i;
for (i = 0; i < nr; i++)
mask |= 1 << (gm204_sor_dp_lane_map(priv, i) >> 3);
mask |= 1 << (gm204_sor_dp_lane_map(disp, i) >> 3);
nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask);
nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000);
nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000);
nv_mask(disp, 0x61c130 + loff, 0x0000000f, mask);
nv_mask(disp, 0x61c034 + soff, 0x80000000, 0x80000000);
nv_wait(disp, 0x61c034 + soff, 0x80000000, 0x00000000);
return 0;
}
......@@ -90,9 +90,9 @@ static int
gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
int ln, int vs, int pe, int pc)
{
struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
struct nvkm_bios *bios = nvkm_bios(priv);
const u32 shift = gm204_sor_dp_lane_map(priv, ln);
struct nv50_disp *disp = (void *)nvkm_disp(outp);
struct nvkm_bios *bios = nvkm_bios(disp);
const u32 shift = gm204_sor_dp_lane_map(disp, ln);
const u32 loff = gm204_sor_loff(outp);
u32 addr, data[4];
u8 ver, hdr, cnt, len;
......@@ -111,16 +111,16 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
return -EINVAL;
ocfg.tx_pu &= 0x0f;
data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(priv, 0x61c130 + loff);
data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(disp, 0x61c130 + loff);
if ((data[2] & 0x00000f00) < (ocfg.tx_pu << 8) || ln == 0)
data[2] = (data[2] & ~0x00000f00) | (ocfg.tx_pu << 8);
nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
nv_wr32(priv, 0x61c130 + loff, data[2]);
data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift);
nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
nv_wr32(disp, 0x61c130 + loff, data[2]);
data[3] = nv_rd32(disp, 0x61c13c + loff) & ~(0x000000ff << shift);
nv_wr32(disp, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c
View file @ fd166a18
......@@ -48,9 +48,9 @@ nv50_sor_power(NV50_DISP_MTHD_V1)
} else
return ret;
nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
nv_wait(priv, 0x61c030 + soff, 0x10000000, 0x00000000);
nv_wait(disp, 0x61c004 + soff, 0x80000000, 0x00000000);
nv_mask(disp, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
nv_wait(disp, 0x61c004 + soff, 0x80000000, 0x00000000);
nv_wait(disp, 0x61c030 + soff, 0x10000000, 0x00000000);
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
View file @ fd166a18
......@@ -156,7 +156,7 @@ nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_disp *pdisp = nvkm_disp(parent);
struct nvkm_disp *disp = nvkm_disp(parent);
struct nv50_sw_cclass *pclass = (void *)oclass;
struct nv50_sw_chan *chan;
int ret, i;
......@@ -166,8 +166,8 @@ nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
for (i = 0; pdisp && i < pdisp->vblank.index_nr; i++) {
ret = nvkm_notify_init(NULL, &pdisp->vblank, pclass->vblank,
for (i = 0; disp && i < disp->vblank.index_nr; i++) {
ret = nvkm_notify_init(NULL, &disp->vblank, pclass->vblank,
false,
&(struct nvif_notify_head_req_v0) {
.head = i,
......
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