Commit fd9470ce authored by Russell King's avatar Russell King Committed by Russell King

Merge branch 'omap2-clock' of...

Merge branch 'omap2-clock' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git

Merge branch 'omap2-clock' into omap-all
parents b8e6c91c e89087c9
...@@ -4,7 +4,8 @@ ...@@ -4,7 +4,8 @@
# Common support # Common support
obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \ obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
devices.o serial.o gpmc.o timer-gp.o devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
clockdomain.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
......
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <asm/io.h> #include <asm/io.h>
#include <mach/clock.h> #include <mach/clock.h>
#include <mach/clockdomain.h>
#include <mach/sram.h> #include <mach/sram.h>
#include <mach/cpu.h> #include <mach/cpu.h>
#include <asm/div64.h> #include <asm/div64.h>
...@@ -62,9 +63,35 @@ ...@@ -62,9 +63,35 @@
u8 cpu_mask; u8 cpu_mask;
/*------------------------------------------------------------------------- /*-------------------------------------------------------------------------
* Omap2 specific clock functions * OMAP2/3 specific clock functions
*-------------------------------------------------------------------------*/ *-------------------------------------------------------------------------*/
/**
* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
* @clk: OMAP clock struct ptr to use
*
* Convert a clockdomain name stored in a struct clk 'clk' into a
* clockdomain pointer, and save it into the struct clk. Intended to be
* called during clk_register(). No return value.
*/
void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;
if (!clk->clkdm_name)
return;
clkdm = clkdm_lookup(clk->clkdm_name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
clk->name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
pr_debug("clock: could not associate clk %s to "
"clkdm %s\n", clk->name, clk->clkdm_name);
}
}
/** /**
* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
* @clk: OMAP clock struct ptr to use * @clk: OMAP clock struct ptr to use
...@@ -308,6 +335,9 @@ void omap2_clk_disable(struct clk *clk) ...@@ -308,6 +335,9 @@ void omap2_clk_disable(struct clk *clk)
_omap2_clk_disable(clk); _omap2_clk_disable(clk);
if (likely((u32)clk->parent)) if (likely((u32)clk->parent))
omap2_clk_disable(clk->parent); omap2_clk_disable(clk->parent);
if (clk->clkdm)
omap2_clkdm_clk_disable(clk->clkdm, clk);
} }
} }
...@@ -324,11 +354,19 @@ int omap2_clk_enable(struct clk *clk) ...@@ -324,11 +354,19 @@ int omap2_clk_enable(struct clk *clk)
return ret; return ret;
} }
if (clk->clkdm)
omap2_clkdm_clk_enable(clk->clkdm, clk);
ret = _omap2_clk_enable(clk); ret = _omap2_clk_enable(clk);
if (unlikely(ret != 0) && clk->parent) { if (unlikely(ret != 0)) {
omap2_clk_disable(clk->parent); if (clk->clkdm)
clk->usecount--; omap2_clkdm_clk_disable(clk->clkdm, clk);
if (clk->parent) {
omap2_clk_disable(clk->parent);
clk->usecount--;
}
} }
} }
......
...@@ -36,6 +36,7 @@ void omap2_clk_disable_unused(struct clk *clk); ...@@ -36,6 +36,7 @@ void omap2_clk_disable_unused(struct clk *clk);
#endif #endif
void omap2_clksel_recalc(struct clk *clk); void omap2_clksel_recalc(struct clk *clk);
void omap2_init_clk_clkdm(struct clk *clk);
void omap2_init_clksel_parent(struct clk *clk); void omap2_init_clksel_parent(struct clk *clk);
u32 omap2_clksel_get_divisor(struct clk *clk); u32 omap2_clksel_get_divisor(struct clk *clk);
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
......
This diff is collapsed.
...@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk) ...@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
{ {
const struct dpll_data *dd; const struct dpll_data *dd;
u32 v;
dd = clk->dpll_data; dd = clk->dpll_data;
cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask), v = __raw_readl(dd->control_reg);
dd->control_reg); v &= ~dd->enable_mask;
v |= clken_bits << __ffs(dd->enable_mask);
__raw_writel(v, dd->control_reg);
} }
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
...@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) ...@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
state <<= dd->idlest_bit; state <<= dd->idlest_bit;
idlest_mask = 1 << dd->idlest_bit; idlest_mask = 1 << dd->idlest_bit;
while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) && while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
i < MAX_DPLL_WAIT_TRIES) { i < MAX_DPLL_WAIT_TRIES) {
i++; i++;
udelay(1); udelay(1);
...@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) ...@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
dd = clk->dpll_data; dd = clk->dpll_data;
v = cm_read_reg(dd->autoidle_reg); v = __raw_readl(dd->autoidle_reg);
v &= dd->autoidle_mask; v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask); v >>= __ffs(dd->autoidle_mask);
...@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) ...@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
static void omap3_dpll_allow_idle(struct clk *clk) static void omap3_dpll_allow_idle(struct clk *clk)
{ {
const struct dpll_data *dd; const struct dpll_data *dd;
u32 v;
if (!clk || !clk->dpll_data) if (!clk || !clk->dpll_data)
return; return;
...@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk) ...@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
* by writing 0x5 instead of 0x1. Add some mechanism to * by writing 0x5 instead of 0x1. Add some mechanism to
* optionally enter this mode. * optionally enter this mode.
*/ */
cm_rmw_reg_bits(dd->autoidle_mask, v = __raw_readl(dd->autoidle_reg);
DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask), v &= ~dd->autoidle_mask;
dd->autoidle_reg); v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg);
} }
/** /**
...@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk) ...@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
static void omap3_dpll_deny_idle(struct clk *clk) static void omap3_dpll_deny_idle(struct clk *clk)
{ {
const struct dpll_data *dd; const struct dpll_data *dd;
u32 v;
if (!clk || !clk->dpll_data) if (!clk || !clk->dpll_data)
return; return;
dd = clk->dpll_data; dd = clk->dpll_data;
cm_rmw_reg_bits(dd->autoidle_mask, v = __raw_readl(dd->autoidle_reg);
DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask), v &= ~dd->autoidle_mask;
dd->autoidle_reg); v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg);
} }
/* Clock control for DPLL outputs */ /* Clock control for DPLL outputs */
...@@ -482,8 +489,10 @@ int __init omap2_clk_init(void) ...@@ -482,8 +489,10 @@ int __init omap2_clk_init(void)
for (clkp = onchip_34xx_clks; for (clkp = onchip_34xx_clks;
clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
clkp++) { clkp++) {
if ((*clkp)->flags & cpu_clkflg) if ((*clkp)->flags & cpu_clkflg) {
clk_register(*clkp); clk_register(*clkp);
omap2_init_clk_clkdm(*clkp);
}
} }
/* REVISIT: Not yet ready for OMAP3 */ /* REVISIT: Not yet ready for OMAP3 */
......
This diff is collapsed.
This diff is collapsed.
/*
* OMAP2/3 clockdomains
*
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008 Nokia Corporation
*
* Written by Paul Walmsley
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
#include <mach/clockdomain.h>
/*
* OMAP2/3-common clockdomains
*/
/* This is an implicit clockdomain - it is never defined as such in TRM */
static struct clockdomain wkup_clkdm = {
.name = "wkup_clkdm",
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};
/*
* 2420-only clockdomains
*/
#if defined(CONFIG_ARCH_OMAP2420)
static struct clockdomain mpu_2420_clkdm = {
.name = "mpu_clkdm",
.pwrdm_name = "mpu_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static struct clockdomain iva1_2420_clkdm = {
.name = "iva1_clkdm",
.pwrdm_name = "dsp_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
#endif /* CONFIG_ARCH_OMAP2420 */
/*
* 2430-only clockdomains
*/
#if defined(CONFIG_ARCH_OMAP2430)
static struct clockdomain mpu_2430_clkdm = {
.name = "mpu_clkdm",
.pwrdm_name = "mpu_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
static struct clockdomain mdm_clkdm = {
.name = "mdm_clkdm",
.pwrdm_name = "mdm_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
#endif /* CONFIG_ARCH_OMAP2430 */
/*
* 24XX-only clockdomains
*/
#if defined(CONFIG_ARCH_OMAP24XX)
static struct clockdomain dsp_clkdm = {
.name = "dsp_clkdm",
.pwrdm_name = "dsp_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
static struct clockdomain gfx_24xx_clkdm = {
.name = "gfx_clkdm",
.pwrdm_name = "gfx_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
static struct clockdomain core_l3_24xx_clkdm = {
.name = "core_l3_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
static struct clockdomain core_l4_24xx_clkdm = {
.name = "core_l4_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
static struct clockdomain dss_24xx_clkdm = {
.name = "dss_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
#endif /* CONFIG_ARCH_OMAP24XX */
/*
* 34xx clockdomains
*/
#if defined(CONFIG_ARCH_OMAP34XX)
static struct clockdomain mpu_34xx_clkdm = {
.name = "mpu_clkdm",
.pwrdm_name = "mpu_pwrdm",
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain neon_clkdm = {
.name = "neon_clkdm",
.pwrdm_name = "neon_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain iva2_clkdm = {
.name = "iva2_clkdm",
.pwrdm_name = "iva2_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain gfx_3430es1_clkdm = {
.name = "gfx_clkdm",
.pwrdm_name = "gfx_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
};
static struct clockdomain sgx_clkdm = {
.name = "sgx_clkdm",
.pwrdm_name = "sgx_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
};
/*
* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
* then that information was removed from the 34xx ES2+ TRM. It is
* unclear whether the core is still there, but the clockdomain logic
* is there, and must be programmed to an appropriate state if the
* CORE clockdomain is to become inactive.
*/
static struct clockdomain d2d_clkdm = {
.name = "d2d_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain core_l3_34xx_clkdm = {
.name = "core_l3_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain core_l4_34xx_clkdm = {
.name = "core_l4_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain dss_34xx_clkdm = {
.name = "dss_clkdm",
.pwrdm_name = "dss_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain cam_clkdm = {
.name = "cam_clkdm",
.pwrdm_name = "cam_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain usbhost_clkdm = {
.name = "usbhost_clkdm",
.pwrdm_name = "usbhost_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
};
static struct clockdomain per_clkdm = {
.name = "per_clkdm",
.pwrdm_name = "per_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain emu_clkdm = {
.name = "emu_clkdm",
.pwrdm_name = "emu_pwrdm",
.flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
#endif /* CONFIG_ARCH_OMAP34XX */
/*
* Clockdomain-powerdomain hwsup dependencies (34XX only)
*/
static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "iva2_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL }
};
/*
*
*/
static struct clockdomain *clockdomains_omap[] = {
&wkup_clkdm,
#ifdef CONFIG_ARCH_OMAP2420
&mpu_2420_clkdm,
&iva1_2420_clkdm,
#endif
#ifdef CONFIG_ARCH_OMAP2430
&mpu_2430_clkdm,
&mdm_clkdm,
#endif
#ifdef CONFIG_ARCH_OMAP24XX
&dsp_clkdm,
&gfx_24xx_clkdm,
&core_l3_24xx_clkdm,
&core_l4_24xx_clkdm,
&dss_24xx_clkdm,
#endif
#ifdef CONFIG_ARCH_OMAP34XX
&mpu_34xx_clkdm,
&neon_clkdm,
&iva2_clkdm,
&gfx_3430es1_clkdm,
&sgx_clkdm,
&d2d_clkdm,
&core_l3_34xx_clkdm,
&core_l4_34xx_clkdm,
&dss_34xx_clkdm,
&cam_clkdm,
&usbhost_clkdm,
&per_clkdm,
&emu_clkdm,
#endif
NULL,
};
#endif
...@@ -63,7 +63,8 @@ ...@@ -63,7 +63,8 @@
#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
/* CM_CLKSTCTRL_MPU */ /* CM_CLKSTCTRL_MPU */
#define OMAP24XX_AUTOSTATE_MPU (1 << 0) #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
/* CM_FCLKEN1_CORE specific bits*/ /* CM_FCLKEN1_CORE specific bits*/
#define OMAP24XX_EN_TV_SHIFT 2 #define OMAP24XX_EN_TV_SHIFT 2
...@@ -238,9 +239,12 @@ ...@@ -238,9 +239,12 @@
#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
/* CM_CLKSTCTRL_CORE */ /* CM_CLKSTCTRL_CORE */
#define OMAP24XX_AUTOSTATE_DSS (1 << 2) #define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
#define OMAP24XX_AUTOSTATE_L4 (1 << 1) #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
#define OMAP24XX_AUTOSTATE_L3 (1 << 0) #define OMAP24XX_AUTOSTATE_L4_SHIFT 1
#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
/* CM_FCLKEN_GFX */ /* CM_FCLKEN_GFX */
#define OMAP24XX_EN_3D_SHIFT 2 #define OMAP24XX_EN_3D_SHIFT 2
...@@ -255,7 +259,8 @@ ...@@ -255,7 +259,8 @@
/* CM_CLKSEL_GFX specific bits */ /* CM_CLKSEL_GFX specific bits */
/* CM_CLKSTCTRL_GFX */ /* CM_CLKSTCTRL_GFX */
#define OMAP24XX_AUTOSTATE_GFX (1 << 0) #define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
/* CM_FCLKEN_WKUP specific bits */ /* CM_FCLKEN_WKUP specific bits */
...@@ -367,8 +372,10 @@ ...@@ -367,8 +372,10 @@
#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
/* CM_CLKSTCTRL_DSP */ /* CM_CLKSTCTRL_DSP */
#define OMAP2420_AUTOSTATE_IVA (1 << 8) #define OMAP2420_AUTOSTATE_IVA_SHIFT 8
#define OMAP24XX_AUTOSTATE_DSP (1 << 0) #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
/* CM_FCLKEN_MDM */ /* CM_FCLKEN_MDM */
/* 2430 only */ /* 2430 only */
...@@ -396,6 +403,7 @@ ...@@ -396,6 +403,7 @@
/* CM_CLKSTCTRL_MDM */ /* CM_CLKSTCTRL_MDM */
/* 2430 only */ /* 2430 only */
#define OMAP2430_AUTOSTATE_MDM (1 << 0) #define OMAP2430_AUTOSTATE_MDM_SHIFT 0
#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
#endif #endif
...@@ -96,7 +96,8 @@ ...@@ -96,7 +96,8 @@
#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
/* CM_CLKSTST_IVA2 */ /* CM_CLKSTST_IVA2 */
#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
/* CM_REVISION specific bits */ /* CM_REVISION specific bits */
...@@ -140,7 +141,8 @@ ...@@ -140,7 +141,8 @@
#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
/* CM_CLKSTST_MPU */ /* CM_CLKSTST_MPU */
#define OMAP3430_CLKACTIVITY_MPU (1 << 0) #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
/* CM_FCLKEN1_CORE specific bits */ /* CM_FCLKEN1_CORE specific bits */
...@@ -300,9 +302,12 @@ ...@@ -300,9 +302,12 @@
#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
/* CM_CLKSTST_CORE */ /* CM_CLKSTST_CORE */
#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
#define OMAP3430_CLKACTIVITY_L4 (1 << 1) #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
#define OMAP3430_CLKACTIVITY_L3 (1 << 0) #define OMAP3430_CLKACTIVITY_L4_SHIFT 1
#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
/* CM_FCLKEN_GFX */ /* CM_FCLKEN_GFX */
#define OMAP3430ES1_EN_3D (1 << 2) #define OMAP3430ES1_EN_3D (1 << 2)
...@@ -323,7 +328,8 @@ ...@@ -323,7 +328,8 @@
#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
/* CM_CLKSTST_GFX */ /* CM_CLKSTST_GFX */
#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
/* CM_FCLKEN_SGX */ /* CM_FCLKEN_SGX */
#define OMAP3430ES2_EN_SGX_SHIFT 1 #define OMAP3430ES2_EN_SGX_SHIFT 1
...@@ -333,6 +339,14 @@ ...@@ -333,6 +339,14 @@
#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
/* CM_CLKSTCTRL_SGX */
#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
/* CM_CLKSTST_SGX */
#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
/* CM_FCLKEN_WKUP specific bits */ /* CM_FCLKEN_WKUP specific bits */
#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9
...@@ -498,7 +512,8 @@ ...@@ -498,7 +512,8 @@
#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
/* CM_CLKSTST_DSS */ /* CM_CLKSTST_DSS */
#define OMAP3430_CLKACTIVITY_DSS (1 << 0) #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
/* CM_FCLKEN_CAM specific bits */ /* CM_FCLKEN_CAM specific bits */
...@@ -522,7 +537,8 @@ ...@@ -522,7 +537,8 @@
#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
/* CM_CLKSTST_CAM */ /* CM_CLKSTST_CAM */
#define OMAP3430_CLKACTIVITY_CAM (1 << 0) #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
/* CM_FCLKEN_PER specific bits */ /* CM_FCLKEN_PER specific bits */
...@@ -598,7 +614,8 @@ ...@@ -598,7 +614,8 @@
#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
/* CM_CLKSTST_PER */ /* CM_CLKSTST_PER */
#define OMAP3430_CLKACTIVITY_PER (1 << 0) #define OMAP3430_CLKACTIVITY_PER_SHIFT 0
#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
/* CM_CLKSEL1_EMU */ /* CM_CLKSEL1_EMU */
#define OMAP3430_DIV_DPLL4_SHIFT 24 #define OMAP3430_DIV_DPLL4_SHIFT 24
...@@ -623,7 +640,8 @@ ...@@ -623,7 +640,8 @@
#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
/* CM_CLKSTST_EMU */ /* CM_CLKSTST_EMU */
#define OMAP3430_CLKACTIVITY_EMU (1 << 0) #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
/* CM_CLKSEL2_EMU specific bits */ /* CM_CLKSEL2_EMU specific bits */
#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
...@@ -673,6 +691,8 @@ ...@@ -673,6 +691,8 @@
#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
/* CM_CLKSTST_USBHOST */
#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
#endif #endif
...@@ -24,6 +24,13 @@ ...@@ -24,6 +24,13 @@
#include <mach/mux.h> #include <mach/mux.h>
#include <mach/omapfb.h> #include <mach/omapfb.h>
#include <mach/powerdomain.h>
#include "powerdomains.h"
#include <mach/clockdomain.h>
#include "clockdomains.h"
extern void omap_sram_init(void); extern void omap_sram_init(void);
extern int omap2_clk_init(void); extern int omap2_clk_init(void);
extern void omap2_check_revision(void); extern void omap2_check_revision(void);
...@@ -101,6 +108,8 @@ void __init omap2_map_common_io(void) ...@@ -101,6 +108,8 @@ void __init omap2_map_common_io(void)
void __init omap2_init_common_hw(void) void __init omap2_init_common_hw(void)
{ {
omap2_mux_init(); omap2_mux_init();
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init(); omap2_clk_init();
/* /*
* Need to Fix this for 2430 * Need to Fix this for 2430
......
This diff is collapsed.
/*
* OMAP2/3 common powerdomain definitions
*
* Copyright (C) 2007-8 Texas Instruments, Inc.
* Copyright (C) 2007-8 Nokia Corporation
*
* Written by Paul Walmsley
* Debugging and integration fixes by Jouni Högander
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS
/*
* This file contains all of the powerdomains that have some element
* of software control for the OMAP24xx and OMAP34XX chips.
*
* A few notes:
*
* This is not an exhaustive listing of powerdomains on the chips; only
* powerdomains that can be controlled in software.
*
* A useful validation rule for struct powerdomain:
* Any powerdomain referenced by a wkdep_srcs or sleepdep_srcs array
* must have a dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really
* just software-controllable dependencies. Non-software-controllable
* dependencies do exist, but they are not encoded below (yet).
*
* 24xx does not support programmable sleep dependencies (SLEEPDEP)
*
*/
/*
* The names for the DSP/IVA2 powerdomains are confusing.
*
* Most OMAP chips have an on-board DSP.
*
* On the 2420, this is a 'C55 DSP called, simply, the DSP. Its
* powerdomain is called the "DSP power domain." On the 2430, the
* on-board DSP is a 'C64 DSP, now called the IVA2 or IVA2.1. Its
* powerdomain is still called the "DSP power domain." On the 3430,
* the DSP is a 'C64 DSP like the 2430, also known as the IVA2; but
* its powerdomain is now called the "IVA2 power domain."
*
* The 2420 also has something called the IVA, which is a separate ARM
* core, and has nothing to do with the DSP/IVA2.
*
* Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM
* address offset is different between the C55 and C64 DSPs.
*
* The overly-specific dep_bit names are due to a bit name collision
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
* value are the same for all powerdomains: 2
*/
/*
* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
* sanity check?
* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
*/
#include <mach/powerdomain.h>
#include "prcm-common.h"
#include "prm.h"
#include "cm.h"
/* OMAP2/3-common powerdomains and wakeup dependencies */
/*
* 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
* 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
*/
static struct pwrdm_dep gfx_sgx_wkdeps[] = {
{
.pwrdm_name = "core_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "iva2_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430)
},
{ NULL },
};
/*
* 3430: CM_SLEEPDEP_CAM: MPU
* 3430ES1: CM_SLEEPDEP_GFX: MPU
* 3430ES2: CM_SLEEPDEP_SGX: MPU
*/
static struct pwrdm_dep cam_gfx_sleepdeps[] = {
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
#include "powerdomains24xx.h"
#include "powerdomains34xx.h"
/*
* OMAP2/3 common powerdomains
*/
/*
* The GFX powerdomain is not present on 3430ES2, but currently we do not
* have a macro to filter it out at compile-time.
*/
static struct powerdomain gfx_pwrdm = {
.name = "gfx_pwrdm",
.prcm_offs = GFX_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430ES1),
.wkdep_srcs = gfx_sgx_wkdeps,
.sleepdep_srcs = cam_gfx_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
},
};
static struct powerdomain wkup_pwrdm = {
.name = "wkup_pwrdm",
.prcm_offs = WKUP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
.dep_bit = OMAP_EN_WKUP_SHIFT,
};
/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap[] __initdata = {
&gfx_pwrdm,
&wkup_pwrdm,
#ifdef CONFIG_ARCH_OMAP24XX
&dsp_pwrdm,
&mpu_24xx_pwrdm,
&core_24xx_pwrdm,
#endif
#ifdef CONFIG_ARCH_OMAP2430
&mdm_pwrdm,
#endif
#ifdef CONFIG_ARCH_OMAP34XX
&iva2_pwrdm,
&mpu_34xx_pwrdm,
&neon_pwrdm,
&core_34xx_pwrdm,
&cam_pwrdm,
&dss_pwrdm,
&per_pwrdm,
&emu_pwrdm,
&sgx_pwrdm,
&usbhost_pwrdm,
#endif
NULL
};
#endif
This diff is collapsed.
This diff is collapsed.
...@@ -312,7 +312,8 @@ ...@@ -312,7 +312,8 @@
#define OMAP3430_ST_GPT2 (1 << 3) #define OMAP3430_ST_GPT2 (1 << 3)
/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
#define OMAP3430_EN_CORE (1 << 0) #define OMAP3430_EN_CORE_SHIFT 0
#define OMAP3430_EN_CORE_MASK (1 << 0)
#endif #endif
...@@ -29,8 +29,10 @@ ...@@ -29,8 +29,10 @@
#define OMAP24XX_WKUP1_EN (1 << 0) #define OMAP24XX_WKUP1_EN (1 << 0)
/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
#define OMAP24XX_EN_MPU (1 << 1) #define OMAP24XX_EN_MPU_SHIFT 1
#define OMAP24XX_EN_CORE (1 << 0) #define OMAP24XX_EN_MPU_MASK (1 << 1)
#define OMAP24XX_EN_CORE_SHIFT 0
#define OMAP24XX_EN_CORE_MASK (1 << 0)
/* /*
* PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
...@@ -140,8 +142,10 @@ ...@@ -140,8 +142,10 @@
/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
/* PM_WKDEP_MPU specific bits */ /* PM_WKDEP_MPU specific bits */
#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5) #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2) #define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
/* PM_EVGENCTRL_MPU specific bits */ /* PM_EVGENCTRL_MPU specific bits */
......
...@@ -68,7 +68,8 @@ ...@@ -68,7 +68,8 @@
#define OMAP3430_VPINIDLE (1 << 0) #define OMAP3430_VPINIDLE (1 << 0)
/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
#define OMAP3430_EN_PER (1 << 7) #define OMAP3430_EN_PER_SHIFT 7
#define OMAP3430_EN_PER_MASK (1 << 7)
/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
#define OMAP3430_MEMORYCHANGE (1 << 3) #define OMAP3430_MEMORYCHANGE (1 << 3)
...@@ -77,7 +78,7 @@ ...@@ -77,7 +78,7 @@
#define OMAP3430_LOGICSTATEST (1 << 2) #define OMAP3430_LOGICSTATEST (1 << 2)
/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) #define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
/* /*
* PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
...@@ -278,8 +279,10 @@ ...@@ -278,8 +279,10 @@
#define OMAP3430_EMULATION_MPU_RST (1 << 11) #define OMAP3430_EMULATION_MPU_RST (1 << 11)
/* PM_WKDEP_MPU specific bits */ /* PM_WKDEP_MPU specific bits */
#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5) #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2) #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
/* PM_EVGENCTRL_MPU */ /* PM_EVGENCTRL_MPU */
#define OMAP3430_OFFLOADMODE_SHIFT 3 #define OMAP3430_OFFLOADMODE_SHIFT 3
......
...@@ -305,7 +305,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) ...@@ -305,7 +305,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
* 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
* PM_WKDEP_PER * PM_WKDEP_PER
*/ */
#define OMAP_EN_WKUP (1 << 4) #define OMAP_EN_WKUP_SHIFT 4
#define OMAP_EN_WKUP_MASK (1 << 4)
/* /*
* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
......
...@@ -29,6 +29,30 @@ config OMAP_DEBUG_LEDS ...@@ -29,6 +29,30 @@ config OMAP_DEBUG_LEDS
depends on OMAP_DEBUG_DEVICES depends on OMAP_DEBUG_DEVICES
default y if LEDS || LEDS_OMAP_DEBUG default y if LEDS || LEDS_OMAP_DEBUG
config OMAP_DEBUG_POWERDOMAIN
bool "Emit debug messages from powerdomain layer"
depends on ARCH_OMAP2 || ARCH_OMAP3
default n
help
Say Y here if you want to compile in powerdomain layer
debugging messages for OMAP2/3. These messages can
provide more detail as to why some powerdomain calls
may be failing, and will also emit a descriptive message
for every powerdomain register write. However, the
extra detail costs some memory.
config OMAP_DEBUG_CLOCKDOMAIN
bool "Emit debug messages from clockdomain layer"
depends on ARCH_OMAP2 || ARCH_OMAP3
default n
help
Say Y here if you want to compile in clockdomain layer
debugging messages for OMAP2/3. These messages can
provide more detail as to why some clockdomain calls
may be failing, and will also emit a descriptive message
for every clockdomain register write. However, the
extra detail costs some memory.
config OMAP_RESET_CLOCKS config OMAP_RESET_CLOCKS
bool "Reset unused clocks during boot" bool "Reset unused clocks during boot"
depends on ARCH_OMAP depends on ARCH_OMAP
......
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
struct module; struct module;
struct clk; struct clk;
struct clockdomain;
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
...@@ -79,6 +80,8 @@ struct clk { ...@@ -79,6 +80,8 @@ struct clk {
u32 clksel_mask; u32 clksel_mask;
const struct clksel *clksel; const struct clksel *clksel;
struct dpll_data *dpll_data; struct dpll_data *dpll_data;
const char *clkdm_name;
struct clockdomain *clkdm;
#else #else
__u8 rate_offset; __u8 rate_offset;
__u8 src_offset; __u8 src_offset;
......
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