Commit fe45174b authored by Maxime Ripard's avatar Maxime Ripard

arm: dts: sunxi: Revert EMAC changes

Since the discussion is not settled yet for the EMAC, and that the release
in getting really close, let's revert the changes for now, and we'll
reintroduce them later.
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 87e1f5e8
...@@ -56,8 +56,6 @@ / { ...@@ -56,8 +56,6 @@ / {
aliases { aliases {
serial0 = &uart0; serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet0 = &emac;
ethernet1 = &xr819; ethernet1 = &xr819;
}; };
...@@ -104,13 +102,6 @@ &ehci1 { ...@@ -104,13 +102,6 @@ &ehci1 {
status = "okay"; status = "okay";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&mmc0 { &mmc0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>; pinctrl-0 = <&mmc0_pins_a>;
......
...@@ -52,7 +52,6 @@ / { ...@@ -52,7 +52,6 @@ / {
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
aliases { aliases {
ethernet0 = &emac;
serial0 = &uart0; serial0 = &uart0;
serial1 = &uart1; serial1 = &uart1;
}; };
...@@ -115,30 +114,12 @@ &ehci2 { ...@@ -115,30 +114,12 @@ &ehci2 {
status = "okay"; status = "okay";
}; };
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
allwinner,leds-active-low;
status = "okay";
};
&ir { &ir {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>; pinctrl-0 = <&ir_pins_a>;
status = "okay"; status = "okay";
}; };
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mmc0 { &mmc0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
......
...@@ -46,10 +46,3 @@ / { ...@@ -46,10 +46,3 @@ / {
model = "FriendlyARM NanoPi NEO"; model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
...@@ -54,7 +54,6 @@ / { ...@@ -54,7 +54,6 @@ / {
aliases { aliases {
serial0 = &uart0; serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet0 = &emac;
ethernet1 = &rtl8189; ethernet1 = &rtl8189;
}; };
...@@ -118,13 +117,6 @@ &ehci1 { ...@@ -118,13 +117,6 @@ &ehci1 {
status = "okay"; status = "okay";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&ir { &ir {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>; pinctrl-0 = <&ir_pins_a>;
......
...@@ -52,7 +52,6 @@ / { ...@@ -52,7 +52,6 @@ / {
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases { aliases {
ethernet0 = &emac;
serial0 = &uart0; serial0 = &uart0;
}; };
...@@ -98,13 +97,6 @@ &ehci1 { ...@@ -98,13 +97,6 @@ &ehci1 {
status = "okay"; status = "okay";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&mmc0 { &mmc0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
......
...@@ -53,11 +53,6 @@ aliases { ...@@ -53,11 +53,6 @@ aliases {
}; };
}; };
&emac {
/* LEDs changed to active high on the plus */
/delete-property/ allwinner,leds-active-low;
};
&mmc1 { &mmc1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>; pinctrl-0 = <&mmc1_pins_a>;
......
...@@ -52,7 +52,6 @@ / { ...@@ -52,7 +52,6 @@ / {
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
aliases { aliases {
ethernet0 = &emac;
serial0 = &uart0; serial0 = &uart0;
}; };
...@@ -114,13 +113,6 @@ &ehci3 { ...@@ -114,13 +113,6 @@ &ehci3 {
status = "okay"; status = "okay";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&ir { &ir {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>; pinctrl-0 = <&ir_pins_a>;
......
...@@ -47,10 +47,6 @@ / { ...@@ -47,10 +47,6 @@ / {
model = "Xunlong Orange Pi Plus / Plus 2"; model = "Xunlong Orange Pi Plus / Plus 2";
compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
aliases {
ethernet0 = &emac;
};
reg_gmac_3v3: gmac-3v3 { reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "gmac-3v3"; regulator-name = "gmac-3v3";
...@@ -78,24 +74,6 @@ &ehci3 { ...@@ -78,24 +74,6 @@ &ehci3 {
status = "okay"; status = "okay";
}; };
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
allwinner,leds-active-low;
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mmc2 { &mmc2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>; pinctrl-0 = <&mmc2_8bit_pins>;
......
...@@ -61,19 +61,3 @@ reg_gmac_3v3: gmac-3v3 { ...@@ -61,19 +61,3 @@ reg_gmac_3v3: gmac-3v3 {
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
}; };
}; };
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
...@@ -391,32 +391,6 @@ timer@01c20c00 { ...@@ -391,32 +391,6 @@ timer@01c20c00 {
clocks = <&osc24M>; clocks = <&osc24M>;
}; };
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
};
};
};
spi0: spi@01c68000 { spi0: spi@01c68000 {
compatible = "allwinner,sun8i-h3-spi"; compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>; reg = <0x01c68000 0x1000>;
......
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