Skip to content

L
linux
Commit ff050ad1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC specific changes from Arnd Bergmann:
 "Lots of changes specific to one of the SoC families.  Some that stick
  out are:

   - mach-qcom gains new features, most importantly SMP support for the
     newer chips (Stephen Boyd, Rohit Vaswani)
   - mvebu gains support for three new SoCs: Armada 375, 380 and 385
     (Thomas Petazzoni and Free-electrons team)
   - SMP support for Rockchips (Heiko Stübner)
   - Lots of i.MX changes (Shawn Guo)
   - Added support for BCM5301x SoC (Hauke Mehrtens)
   - Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn
     and Sebastian Hesselbarth doing the final part of a long journey)
   - Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd
     Bergmann)"

* tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits)
  ARM: sunxi: Select HAVE_ARM_ARCH_TIMER
  ARM: cache-tauros2: remove ARMv6 code
  ARM: mvebu: don't select CONFIG_NEON
  ARM: davinci: fix DT booting with default defconfig
  ARM: configs: bcm_defconfig: enable bcm590xx regulator support
  ARM: davinci: remove tnetv107x support
  MAINTAINERS: Update ARM STi maintainers
  ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE
  ARM: bcm21664: Add board support.
  ARM: sunxi: Add the new watchog compatibles to the reboot code
  ARM: enable ARM_HAS_SG_CHAIN for multiplatform
  ARM: davinci: remove da8xx_omapl_defconfig
  ARM: davinci: da8xx: fix multiple watchdog device registration
  ARM: davinci: add da8xx specific configs to davinci_all_defconfig
  ARM: davinci: enable da8xx build concurrently with older devices
  ARM: BCM5301X: workaround suppress fault
  ARM: BCM5301X: add early debugging support
  ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU
  ARM: mach-bcm: Remove GENERIC_TIME
  ARM: shmobile: APMU: Fix warnings due to improper printk formats
  ...
parents dfc25e45 9233087d
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 3918 additions and 3415 deletions
Documentation/arm/Marvell/README
View file @ ff050ad1
......@@ -83,14 +83,24 @@ EBU Armada family
88F6710
88F6707
88F6W11
Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf
Armada 375 Flavors:
88F6720
Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA_375_SoC-01_product_brief.pdf
Armada 380/385 Flavors:
88F6810
88F6820
88F6828
Armada XP Flavors:
MV78230
MV78260
MV78460
NOTE: not to be confused with the non-SMP 78xx0 SoCs
Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
No public datasheet available.
Core: Sheeva ARMv7 compatible
......
Documentation/devicetree/bindings/arm/armada-375.txt 0 → 100644
View file @ ff050ad1
Marvell Armada 375 Platforms Device Tree Bindings
-------------------------------------------------
Boards with a SoC of the Marvell Armada 375 family shall have the
following property:
Required root node property:
compatible: must contain "marvell,armada375"
Documentation/devicetree/bindings/arm/armada-38x.txt 0 → 100644
View file @ ff050ad1
Marvell Armada 38x Platforms Device Tree Bindings
-------------------------------------------------
Boards with a SoC of the Marvell Armada 38x family shall have the
following property:
Required root node property:
- compatible: must contain either "marvell,armada380" or
"marvell,armada385" depending on the variant of the SoC being used.
Documentation/devicetree/bindings/arm/bcm4708.txt 0 → 100644
View file @ ff050ad1
Broadcom BCM4708 device tree bindings
-------------------------------------------
Boards with the BCM4708 SoC shall have the following properties:
Required root node property:
compatible = "brcm,bcm4708";
Documentation/devicetree/bindings/arm/cpus.txt
View file @ ff050ad1
......@@ -180,7 +180,11 @@ nodes to be present and contain the properties described below.
be one of:
"spin-table"
"psci"
# On ARM 32-bit systems this property is optional.
# On ARM 32-bit systems this property is optional and
can be one of:
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
- cpu-release-addr
Usage: required for systems that have an "enable-method"
......@@ -191,6 +195,21 @@ nodes to be present and contain the properties described below.
property identifying a 64-bit zero-initialised
memory location.
- qcom,saw
Usage: required for systems that have an "enable-method"
property value of "qcom,kpss-acc-v1" or
"qcom,kpss-acc-v2"
Value type: <phandle>
Definition: Specifies the SAW[1] node associated with this CPU.
- qcom,acc
Usage: required for systems that have an "enable-method"
property value of "qcom,kpss-acc-v1" or
"qcom,kpss-acc-v2"
Value type: <phandle>
Definition: Specifies the ACC[2] node associated with this CPU.
Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {
......@@ -382,3 +401,7 @@ cpus {
cpu-release-addr = <0 0x20000000>;
};
};
--
[1] arm/msm/qcom,saw2.txt
[2] arm/msm/qcom,kpss-acc.txt
Documentation/devicetree/bindings/arm/mrvl/feroceon.txt 0 → 100644
View file @ ff050ad1
* Marvell Feroceon Cache
Required properties:
- compatible : Should be either "marvell,feroceon-cache" or
"marvell,kirkwood-cache".
Optional properties:
- reg : Address of the L2 cache control register. Mandatory for
"marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
Example:
l2: l2-cache@20128 {
compatible = "marvell,kirkwood-cache";
reg = <0x20128 0x4>;
};
Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt 0 → 100644
View file @ ff050ad1
Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: should be one of:
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the first element specifies the base address and size of
the register region. An optional second element specifies
the base address and size of the alias register region.
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
};
Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt 0 → 100644
View file @ ff050ad1
SPM AVS Wrapper 2 (SAW2)
The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
micro-controller that transitions a piece of hardware (like a processor or
subsystem) into and out of low power modes via a direct connection to
the PMIC. It can also be wired up to interact with other processors in the
system, notifying them when a low power state is entered or exited.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: shall contain "qcom,saw2". A more specific value should be
one of:
"qcom,saw2-v1"
"qcom,saw2-v1.1"
"qcom,saw2-v2"
"qcom,saw2-v2.1"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the first element specifies the base address and size of
the register region. An optional second element specifies
the base address and size of the alias register region.
Example:
regulator@2099000 {
compatible = "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
};
Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
View file @ ff050ad1
MVEBU System Controller
-----------------------
MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
Required properties:
- compatible: one of:
- "marvell,orion-system-controller"
- "marvell,armada-370-xp-system-controller"
- "marvell,armada-375-system-controller"
- reg: Should contain system controller registers location and length.
Example:
......
Documentation/devicetree/bindings/arm/rockchip/pmu.txt 0 → 100644
View file @ ff050ad1
Rockchip power-management-unit:
-------------------------------
The pmu is used to turn off and on different power domains of the SoCs
This includes the power to the CPU cores.
Required node properties:
- compatible value : = "rockchip,rk3066-pmu";
- reg : physical base address and the size of the registers window
Example:
pmu@20004000 {
compatible = "rockchip,rk3066-pmu";
reg = <0x20004000 0x100>;
};
Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt 0 → 100644
View file @ ff050ad1
Rockchip SRAM for smp bringup:
------------------------------
Rockchip's smp-capable SoCs use the first part of the sram for the bringup
of the cores. Once the core gets powered up it executes the code that is
residing at the very beginning of the sram.
Therefore a reserved section sub-node has to be added to the mmio-sram
declaration.
Required sub-node properties:
- compatible : should be "rockchip,rk3066-smp-sram"
The rest of the properties should follow the generic mmio-sram discription
found in ../../misc/sram.txt
Example:
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
smp-sram@10080000 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x10080000 0x50>;
};
};
Documentation/devicetree/bindings/bus/imx-weim.txt
View file @ ff050ad1
......@@ -8,7 +8,12 @@ The actual devices are instantiated from the child nodes of a WEIM node.
Required properties:
- compatible: Should be set to "fsl,<soc>-weim"
- compatible: Should contain one of the following:
"fsl,imx1-weim"
"fsl,imx27-weim"
"fsl,imx51-weim"
"fsl,imx50-weim"
"fsl,imx6q-weim"
- reg: A resource specifier for the register space
(see the example below)
- clocks: the clock, see the example below.
......@@ -19,6 +24,26 @@ Required properties:
<cs-number> 0 <physical address of mapping> <size>
Optional properties:
- fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
devices, it should be the phandle to the system General
Purpose Register controller that contains WEIM CS GPR
register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
should be set up as one of the following 4 possible
values depending on the CS space configuration.
IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
---------------------------------------------
05 128M 0M 0M 0M
033 64M 64M 0M 0M
0113 64M 32M 32M 0M
01111 32M 32M 32M 32M
In case that the property is absent, the reset value or
what bootloader sets up in IOMUXC_GPR1[11:0] will be
used.
Timing property for child nodes. It is mandatory, not optional.
- fsl,weim-cs-timing: The timing array, contains timing values for the
......@@ -43,6 +68,7 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
fsl,weim-cs-gpr = <&gpr>;
nor@0,0 {
compatible = "cfi-flash";
......
Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt 0 → 100644
View file @ ff050ad1
Cirrus Logic CLPS711X Interrupt Controller
Required properties:
- compatible: Should be "cirrus,clps711x-intc".
- reg: Specifies base physical address of the registers set.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
The interrupt sources are as follows:
ID Name Description
---------------------------
1: BLINT Battery low (FIQ)
3: MCINT Media changed (FIQ)
4: CSINT CODEC sound
5: EINT1 External 1
6: EINT2 External 2
7: EINT3 External 3
8: TC1OI TC1 under flow
9: TC2OI TC2 under flow
10: RTCMI RTC compare match
11: TINT 64Hz tick
12: UTXINT1 UART1 transmit FIFO half empty
13: URXINT1 UART1 receive FIFO half full
14: UMSINT UART1 modem status changed
15: SSEOTI SSI1 end of transfer
16: KBDINT Keyboard
17: SS2RX SSI2 receive FIFO half or greater full
18: SS2TX SSI2 transmit FIFO less than half empty
28: UTXINT2 UART2 transmit FIFO half empty
29: URXINT2 UART2 receive FIFO half full
32: DAIINT DAI interface (FIQ)
Example:
intc: interrupt-controller {
compatible = "cirrus,clps711x-intc";
reg = <0x80000000 0x4000>;
interrupt-controller;
#interrupt-cells = <1>;
};
MAINTAINERS
View file @ ff050ad1
......@@ -1291,13 +1291,21 @@ S: Maintained
F: drivers/clk/socfpga/
ARM/STI ARCHITECTURE
M: Srinivas Kandagatla <srinivas.kandagatla@st.com>
M: Stuart Menefy <stuart.menefy@st.com>
M: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
M: Maxime Coquelin <maxime.coquelin@st.com>
M: Patrice Chotard <patrice.chotard@st.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: kernel@stlinux.com
W: http://www.stlinux.com
S: Maintained
F: arch/arm/mach-sti/
F: arch/arm/boot/dts/sti*
F: drivers/clocksource/arm_global_timer.c
F: drivers/reset/sti/
F: drivers/pinctrl/pinctrl-st.c
F: drivers/media/rc/st_rc.c
F: drivers/i2c/busses/i2c-st.c
F: drivers/tty/serial/st-asc.c
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
......@@ -1907,6 +1915,14 @@ F: arch/arm/boot/dts/bcm2835*
F: arch/arm/configs/bcm2835_defconfig
F: drivers/*/*bcm2835*
BROADCOM BCM5301X ARM ARCHICTURE
M: Hauke Mehrtens <hauke@hauke-m.de>
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: arch/arm/mach-bcm/bcm_5301x.c
F: arch/arm/boot/dts/bcm5301x.dtsi
F: arch/arm/boot/dts/bcm470*
BROADCOM TG3 GIGABIT ETHERNET DRIVER
M: Nithin Nayak Sujir <nsujir@broadcom.com>
M: Michael Chan <mchan@broadcom.com>
......
arch/arm/Kconfig
View file @ ff050ad1
......@@ -310,6 +310,7 @@ config ARCH_MULTIPLATFORM
bool "Allow multiple platforms to be selected"
depends on MMU
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR
select COMMON_CLK
......@@ -393,8 +394,6 @@ config ARCH_CLPS711X
select CPU_ARM720T
select GENERIC_CLOCKEVENTS
select MFD_SYSCON
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
help
Support for Cirrus Logic 711x/721x/731x based boards.
......@@ -909,7 +908,7 @@ config ARCH_MULTI_V5
bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
depends on !ARCH_MULTI_V6_V7
select ARCH_MULTI_V4_V5
select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
......
arch/arm/Kconfig.debug
View file @ ff050ad1
......@@ -106,9 +106,14 @@ choice
depends on ARCH_BCM2835
select DEBUG_UART_PL01X
config DEBUG_BCM_5301X
bool "Kernel low-level debugging on BCM5301X UART1"
depends on ARCH_BCM_5301X
select DEBUG_UART_PL01X
config DEBUG_BCM_KONA_UART
bool "Kernel low-level debugging messages via BCM KONA UART"
depends on ARCH_BCM
depends on ARCH_BCM_MOBILE
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
......@@ -171,15 +176,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to UART0 serial port on DaVinci DMx devices.
config DEBUG_DAVINCI_TNETV107X_UART1
bool "Kernel low-level debugging on DaVinci TNETV107x using UART1"
depends on ARCH_DAVINCI_TNETV107X
select DEBUG_UART_8250
help
Say Y here if you want the debug print routines to direct
their output to UART1 serial port on DaVinci TNETV107X
devices.
config DEBUG_ZYNQ_UART0
bool "Kernel low-level debugging on Xilinx Zynq using UART0"
depends on ARCH_ZYNQ
......@@ -1014,7 +1010,6 @@ config DEBUG_UART_PHYS
default 0x02530c00 if DEBUG_KEYSTONE_UART0
default 0x02531000 if DEBUG_KEYSTONE_UART1
default 0x03010fe0 if ARCH_RPC
default 0x08108300 if DEBUG_DAVINCI_TNETV107X_UART1
default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \
DEBUG_VEXPRESS_UART0_CA9
default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
......@@ -1023,6 +1018,7 @@ config DEBUG_UART_PHYS
default 0x101f1000 if ARCH_VERSATILE
default 0x101fb000 if DEBUG_NOMADIK_UART
default 0x16000000 if ARCH_INTEGRATOR
default 0x18000300 if DEBUG_BCM_5301X
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
default 0x20060000 if DEBUG_RK29_UART0
default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
......@@ -1071,6 +1067,7 @@ config DEBUG_UART_VIRT
default 0xf0009000 if DEBUG_CNS3XXX
default 0xf01fb000 if DEBUG_NOMADIK_UART
default 0xf0201000 if DEBUG_BCM2835
default 0xf1000300 if DEBUG_BCM_5301X
default 0xf11f1000 if ARCH_VERSATILE
default 0xf1600000 if ARCH_INTEGRATOR
default 0xf1c28000 if DEBUG_SUNXI_UART0
......@@ -1110,7 +1107,6 @@ config DEBUG_UART_VIRT
default 0xfed12000 if ARCH_KIRKWOOD
default 0xfedc0000 if ARCH_EP93XX
default 0xfee003f8 if FOOTBRIDGE
default 0xfee08300 if DEBUG_DAVINCI_TNETV107X_UART1
default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xfee82340 if ARCH_IOP13XX
......@@ -1135,7 +1131,7 @@ config DEBUG_UART_8250_WORD
default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
ARCH_KEYSTONE || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || \
DEBUG_BCM_KONA_UART
config DEBUG_UART_8250_FLOW_CONTROL
......
arch/arm/boot/dts/Makefile
View file @ ff050ad1
......@@ -59,7 +59,7 @@ dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2cd-google-chromecast.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
dove-cubox.dtb \
dove-d2plug.dtb \
dove-d3plug.dtb \
......@@ -86,8 +86,8 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
integratorcp.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
kirkwood := \
kirkwood-cloudbox.dtb \
kirkwood-db-88f6281.dtb \
kirkwood-db-88f6282.dtb \
kirkwood-dns320.dtb \
......@@ -121,6 +121,9 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
kirkwood-topkick.dtb \
kirkwood-ts219-6281.dtb \
kirkwood-ts219-6282.dtb
dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood)
dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood)
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
......
arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
View file @ ff050ad1
......@@ -122,4 +122,66 @@ button@2 {
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
};
};
dsa@0 {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
dsa,ethernet = <&eth0>;
dsa,mii-bus = <&ethphy0>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0>; /* MDIO address 0, switch 0 in tree */
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "cpu";
};
};
};
};
&mdio {
status = "okay";
ethphy0: ethernet-phy@ff {
reg = <0xff>; /* No phy attached */
speed = <1000>;
duplex = <1>;
};
};
&eth0 {
status = "okay";
ethernet0-port@0 {
phy-handle = <&ethphy0>;
};
};
arch/arm/boot/dts/qcom-msm8960.dtsi
View file @ ff050ad1
......@@ -9,6 +9,12 @@ / {
compatible = "qcom,msm8960";
interrupt-parent = <&intc>;
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <1 10 0x304>;
qcom,no-pc-write;
};
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
......
arch/arm/boot/dts/qcom-msm8974.dtsi
View file @ ff050ad1
......@@ -9,6 +9,11 @@ / {
compatible = "qcom,msm8974";
interrupt-parent = <&intc>;
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <1 7 0xf04>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm/boot/dts/rk3066a.dtsi
View file @ ff050ad1
......@@ -64,6 +64,19 @@ timer@2000e000 {
clock-names = "timer", "pclk";
};
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x10000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x0 0x50>;
};
};
pinctrl@20008000 {
compatible = "rockchip,rk3066a-pinctrl";
reg = <0x20008000 0x150>;
......
arch/arm/boot/dts/rk3188.dtsi
View file @ ff050ad1
......@@ -60,6 +60,19 @@ local-timer@1013c600 {
interrupts = <GIC_PPI 13 0xf04>;
};
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x8000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x8000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x0 0x50>;
};
};
pinctrl@20008000 {
compatible = "rockchip,rk3188-pinctrl";
reg = <0x20008000 0xa0>,
......
arch/arm/boot/dts/rk3xxx.dtsi
View file @ ff050ad1
......@@ -26,6 +26,16 @@ soc {
compatible = "simple-bus";
ranges;
scu@1013c000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1013c000 0x100>;
};
pmu@20004000 {
compatible = "rockchip,rk3066-pmu";
reg = <0x20004000 0x100>;
};
gic: interrupt-controller@1013d000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
......
arch/arm/configs/bcm_defconfig
View file @ ff050ad1
......@@ -79,6 +79,13 @@ CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
# CONFIG_HWMON is not set
CONFIG_MFD_BCM590XX=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
CONFIG_REGULATOR_USERSPACE_CONSUMER=y
CONFIG_REGULATOR_BCM590XX=y
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
......
arch/arm/configs/da8xx_omapl_defconfig deleted 100644 → 0
View file @ dfc25e45
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_DAVINCI=y
CONFIG_ARCH_DAVINCI_DA830=y
CONFIG_ARCH_DAVINCI_DA850=y
CONFIG_MACH_DA8XX_DT=y
CONFIG_MACH_MITYOMAPL138=y
CONFIG_MACH_OMAPL138_HAWKBOARD=y
CONFIG_DAVINCI_RESET_CLOCKS=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_LEDS=y
CONFIG_USE_OF=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
CONFIG_CPU_IDLE=y
CONFIG_PM_RUNTIME=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_LRO is not set
CONFIG_NETFILTER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FW_LOADER is not set
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m
CONFIG_NETDEVICES=y
CONFIG_TUN=m
CONFIG_LXT_PHY=y
CONFIG_LSI_ET1011C_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_TI_DAVINCI_EMAC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_NETCONSOLE=y
CONFIG_NETPOLL_TRAP=y
CONFIG_INPUT_MOUSEDEV=m
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_EVBUG=m
CONFIG_KEYBOARD_ATKBD=m
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_XTKBD=m
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIO_LIBPS2=y
# CONFIG_VT_CONSOLE is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DAVINCI=y
CONFIG_PINCTRL_SINGLE=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_DUMMY=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_FB=y
CONFIG_FB_DA8XX=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SND=m
CONFIG_SND_SOC=m
CONFIG_SND_DAVINCI_SOC=m
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_DMADEVICES=y
CONFIG_TI_EDMA=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_XFS_FS=m
CONFIG_INOTIFY=y
CONFIG_AUTOFS4_FS=m
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_MINIX_FS=m
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=m
CONFIG_NFSD_V3=y
CONFIG_SMB_FS=m
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=m
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=m
CONFIG_CRC_T10DIF=m
arch/arm/configs/davinci_all_defconfig
View file @ ff050ad1
......@@ -20,9 +20,14 @@ CONFIG_ARCH_DAVINCI_DM644x=y
CONFIG_ARCH_DAVINCI_DM355=y
CONFIG_ARCH_DAVINCI_DM646x=y
CONFIG_ARCH_DAVINCI_DM365=y
CONFIG_ARCH_DAVINCI_DA830=y
CONFIG_ARCH_DAVINCI_DA850=y
CONFIG_MACH_DA8XX_DT=y
CONFIG_MACH_SFFSDR=y
CONFIG_MACH_NEUROS_OSD2=y
CONFIG_MACH_DM355_LEOPARD=y
CONFIG_MACH_MITYOMAPL138=y
CONFIG_MACH_OMAPL138_HAWKBOARD=y
CONFIG_DAVINCI_MUX_DEBUG=y
CONFIG_DAVINCI_MUX_WARNINGS=y
CONFIG_DAVINCI_RESET_CLOCKS=y
......@@ -32,8 +37,18 @@ CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_LEDS=y
CONFIG_USE_OF=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
CONFIG_CPU_IDLE=y
CONFIG_PM_RUNTIME=y
CONFIG_NET=y
CONFIG_PACKET=y
......@@ -57,6 +72,7 @@ CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_NAND=m
CONFIG_MTD_NAND_DAVINCI=m
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
......@@ -71,6 +87,7 @@ CONFIG_TUN=m
CONFIG_LXT_PHY=y
CONFIG_LSI_ET1011C_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_TI_DAVINCI_EMAC=y
CONFIG_DM9000=y
# CONFIG_NETDEV_1000 is not set
......@@ -97,15 +114,21 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=3
# CONFIG_HW_RANDOM is not set
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DAVINCI=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_GPIO_PCF857X=y
CONFIG_WATCHDOG=y
CONFIG_DAVINCI_WATCHDOG=m
CONFIG_MFD_DM355EVM_MSP=y
CONFIG_TPS6507X=y
CONFIG_VIDEO_OUTPUT_CONTROL=m
CONFIG_REGULATOR=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_FB=y
CONFIG_FB_DA8XX=y
CONFIG_FIRMWARE_EDID=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
......
arch/arm/configs/imx_v4_v5_defconfig
View file @ ff050ad1
......@@ -154,6 +154,7 @@ CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
......
arch/arm/configs/imx_v6_v7_defconfig
View file @ ff050ad1
......@@ -39,6 +39,8 @@ CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y
CONFIG_SOC_VF610=y
CONFIG_PCI=y
CONFIG_PCI_IMX6=y
CONFIG_SMP=y
CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT_VOLUNTARY=y
......@@ -165,6 +167,7 @@ CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ANATOP=y
CONFIG_REGULATOR_DA9052=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_PFUZE100=y
......@@ -186,6 +189,7 @@ CONFIG_LCD_L4F00242T03=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=y
......@@ -211,6 +215,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
......@@ -225,6 +230,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y
CONFIG_RTC_DRV_SNVS=y
......@@ -277,6 +283,7 @@ CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_UTF8=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_PROVE_LOCKING=y
......
arch/arm/configs/multi_v7_defconfig
View file @ ff050ad1
......@@ -11,6 +11,7 @@ CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM_5301X=y
CONFIG_ARCH_BCM_MOBILE=y
CONFIG_ARCH_BERLIN=y
CONFIG_MACH_BERLIN_BG2=y
......@@ -55,6 +56,7 @@ CONFIG_ARCH_VEXPRESS_CA9X4=y
CONFIG_ARCH_VIRT=y
CONFIG_ARCH_WM8850=y
CONFIG_ARCH_ZYNQ=y
CONFIG_NEON=y
CONFIG_TRUSTED_FOUNDATIONS=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
......
arch/arm/configs/mvebu_defconfig
View file @ ff050ad1
......@@ -11,6 +11,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_NEON=y
# CONFIG_CACHE_L2X0 is not set
# CONFIG_SWP_EMULATE is not set
CONFIG_PCI=y
......
arch/arm/configs/omap2plus_defconfig
View file @ ff050ad1
......@@ -28,6 +28,7 @@ CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y
CONFIG_SOC_OMAP5=y
CONFIG_SOC_AM33XX=y
CONFIG_SOC_AM43XX=y
CONFIG_SOC_DRA7XX=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
......
arch/arm/firmware/Kconfig
View file @ ff050ad1
......@@ -11,6 +11,7 @@ menu "Firmware options"
config TRUSTED_FOUNDATIONS
bool "Trusted Foundations secure monitor support"
depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
default y
help
Some devices (including most Tegra-based consumer devices on the
market) are booted with the Trusted Foundations secure monitor
......@@ -20,7 +21,7 @@ config TRUSTED_FOUNDATIONS
This option allows the kernel to invoke the secure monitor whenever
required on devices using Trusted Foundations. See
arch/arm/include/asm/trusted_foundations.h or the
tl,trusted-foundations device tree binding documentation for details
tlm,trusted-foundations device tree binding documentation for details
on how to use it.
Say n if you don't know what this is about.
......
arch/arm/firmware/trusted_foundations.c
View file @ ff050ad1
......@@ -22,6 +22,15 @@
#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
#define TF_CPU_PM 0xfffffffc
#define TF_CPU_PM_S3 0xffffffe3
#define TF_CPU_PM_S2 0xffffffe6
#define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5
#define TF_CPU_PM_S1 0xffffffe4
#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
static unsigned long cpu_boot_addr;
static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
{
asm volatile(
......@@ -41,13 +50,22 @@ static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
{
tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0);
cpu_boot_addr = boot_addr;
tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
return 0;
}
static int tf_prepare_idle(void)
{
tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr);
return 0;
}
static const struct firmware_ops trusted_foundations_ops = {
.set_cpu_boot_addr = tf_set_cpu_boot_addr,
.prepare_idle = tf_prepare_idle,
};
void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
......
arch/arm/include/asm/firmware.h
View file @ ff050ad1
......@@ -21,6 +21,10 @@
* A filled up structure can be registered with register_firmware_ops().
*/
struct firmware_ops {
/*
* Inform the firmware we intend to enter CPU idle mode
*/
int (*prepare_idle)(void);
/*
* Enters CPU idle mode
*/
......
arch/arm/plat-orion/include/plat/cache-feroceon-l2.h → arch/arm/include/asm/hardware/cache-feroceon-l2.h
View file @ ff050ad1
/*
* arch/arm/plat-orion/include/plat/cache-feroceon-l2.h
* arch/arm/include/asm/hardware/cache-feroceon-l2.h
*
* Copyright (C) 2008 Marvell Semiconductor
*
......@@ -9,3 +9,5 @@
*/
extern void __init feroceon_l2_init(int l2_wt_override);
extern int __init feroceon_of_init(void);
arch/arm/include/asm/smp.h
View file @ ff050ad1
......@@ -115,6 +115,15 @@ struct smp_operations {
#endif
};
struct of_cpu_method {
const char *method;
struct smp_operations *ops;
};
#define CPU_METHOD_OF_DECLARE(name, _method, _ops) \
static const struct of_cpu_method __cpu_method_of_table_##name \
__used __section(__cpu_method_of_table) \
= { .method = _method, .ops = _ops }
/*
* set platform specific SMP operations
*/
......
arch/arm/include/asm/trusted_foundations.h
View file @ ff050ad1
......@@ -30,6 +30,8 @@
#include <linux/printk.h>
#include <linux/bug.h>
#include <linux/of.h>
#include <linux/cpu.h>
#include <linux/smp.h>
struct trusted_foundations_platform_data {
unsigned int version_major;
......@@ -47,10 +49,13 @@ static inline void register_trusted_foundations(
struct trusted_foundations_platform_data *pd)
{
/*
* If we try to register TF, this means the system needs it to continue.
* Its absence if thus a fatal error.
* If the system requires TF and we cannot provide it, continue booting
* but disable features that cannot be provided.
*/
panic("No support for Trusted Foundations, stopping...\n");
pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
pr_err("Secondary processors as well as CPU PM will be disabled.\n");
setup_max_cpus = 0;
cpu_idle_poll_ctrl(true);
}
static inline void of_register_trusted_foundations(void)
......@@ -59,7 +64,7 @@ static inline void of_register_trusted_foundations(void)
* If we find the target should enable TF but does not support it,
* fail as the system won't be able to do much anyway
*/
if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations"))
if (of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations"))
register_trusted_foundations(NULL);
}
#endif /* CONFIG_TRUSTED_FOUNDATIONS */
......
arch/arm/kernel/devtree.c
View file @ ff050ad1
......@@ -18,6 +18,7 @@
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/smp.h>
#include <asm/cputype.h>
#include <asm/setup.h>
......@@ -63,6 +64,34 @@ void __init arm_dt_memblock_reserve(void)
}
}
#ifdef CONFIG_SMP
extern struct of_cpu_method __cpu_method_of_table_begin[];
extern struct of_cpu_method __cpu_method_of_table_end[];
static int __init set_smp_ops_by_method(struct device_node *node)
{
const char *method;
struct of_cpu_method *m = __cpu_method_of_table_begin;
if (of_property_read_string(node, "enable-method", &method))
return 0;
for (; m < __cpu_method_of_table_end; m++)
if (!strcmp(m->method, method)) {
smp_set_ops(m->ops);
return 1;
}
return 0;
}
#else
static inline int set_smp_ops_by_method(struct device_node *node)
{
return 1;
}
#endif
/*
* arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
* and builds the cpu logical map array containing MPIDR values related to
......@@ -79,6 +108,7 @@ void __init arm_dt_init_cpu_maps(void)
* read as 0.
*/
struct device_node *cpu, *cpus;
int found_method = 0;
u32 i, j, cpuidx = 1;
u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
......@@ -150,8 +180,18 @@ void __init arm_dt_init_cpu_maps(void)
}
tmp_map[i] = hwid;
if (!found_method)
found_method = set_smp_ops_by_method(cpu);
}
/*
* Fallback to an enable-method in the cpus node if nothing found in
* a cpu node.
*/
if (!found_method)
set_smp_ops_by_method(cpus);
if (!bootcpu_valid) {
pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
return;
......
arch/arm/mach-bcm/Kconfig
View file @ ff050ad1
......@@ -43,6 +43,32 @@ config ARCH_BCM2835
This enables support for the Broadcom BCM2835 SoC. This SoC is
used in the Raspberry Pi and Roku 2 devices.
config ARCH_BCM_5301X
bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
depends on MMU
select ARM_GIC
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
select MIGHT_HAVE_PCI
help
Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
This is a network SoC line mostly used in home routers and
wifi access points, it's internal name is Northstar.
This inclused the following SoC: BCM53010, BCM53011, BCM53012,
BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
BCM4708 and BCM4709.
Do not confuse this with the BCM4760 which is a totally
different SoC or with the older BCM47XX and BCM53XX based
network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
endmenu
endif
arch/arm/mach-bcm/Makefile
View file @ ff050ad1
#
# Copyright (C) 2012-2013 Broadcom Corporation
# Copyright (C) 2012-2014 Broadcom Corporation
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
......@@ -10,8 +10,10 @@
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o board_bcm21664.o \
bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
arch/arm/mach-bcm/bcm_5301x.c 0 → 100644
View file @ ff050ad1
/*
* Broadcom BCM470X / BCM5301X ARM platform code.
*
* Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
#include <linux/of_platform.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/siginfo.h>
#include <asm/signal.h>
static bool first_fault = true;
static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
struct pt_regs *regs)
{
if (fsr == 0x1c06 && first_fault) {
first_fault = false;
/*
* These faults with code 0x1c06 happens for no good reason,
* possibly left over from the CFE boot loader.
*/
pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
addr, fsr);
/* Returning non-zero causes fault display and panic */
return 0;
}
/* Others should cause a fault */
return 1;
}
static void __init bcm5301x_init_early(void)
{
/* Install our hook */
hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
"imprecise external abort");
}
static void __init bcm5301x_dt_init(void)
{
l2x0_of_init(0, ~0UL);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char __initconst *bcm5301x_dt_compat[] = {
"brcm,bcm4708",
NULL,
};
DT_MACHINE_START(BCM5301X, "BCM5301X")
.init_early = bcm5301x_init_early,
.init_machine = bcm5301x_dt_init,
.dt_compat = bcm5301x_dt_compat,
MACHINE_END
arch/arm/mach-bcm/board_bcm21664.c 0 → 100644
View file @ ff050ad1
/*
* Copyright (C) 2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clocksource.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "bcm_kona_smc.h"
#include "kona.h"
#define RSTMGR_DT_STRING "brcm,bcm21664-resetmgr"
#define RSTMGR_REG_WR_ACCESS_OFFSET 0
#define RSTMGR_REG_CHIP_SOFT_RST_OFFSET 4
#define RSTMGR_WR_PASSWORD 0xa5a5
#define RSTMGR_WR_PASSWORD_SHIFT 8
#define RSTMGR_WR_ACCESS_ENABLE 1
static void bcm21664_restart(enum reboot_mode mode, const char *cmd)
{
void __iomem *base;
struct device_node *resetmgr;
resetmgr = of_find_compatible_node(NULL, NULL, RSTMGR_DT_STRING);
if (!resetmgr) {
pr_emerg("Couldn't find " RSTMGR_DT_STRING "\n");
return;
}
base = of_iomap(resetmgr, 0);
if (!base) {
pr_emerg("Couldn't map " RSTMGR_DT_STRING "\n");
return;
}
/*
* A soft reset is triggered by writing a 0 to bit 0 of the soft reset
* register. To write to that register we must first write the password
* and the enable bit in the write access enable register.
*/
writel((RSTMGR_WR_PASSWORD << RSTMGR_WR_PASSWORD_SHIFT) |
RSTMGR_WR_ACCESS_ENABLE,
base + RSTMGR_REG_WR_ACCESS_OFFSET);
writel(0, base + RSTMGR_REG_CHIP_SOFT_RST_OFFSET);
/* Wait for reset */
while (1);
}
static void __init bcm21664_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL,
&platform_bus);
kona_l2_cache_init();
}
static const char * const bcm21664_dt_compat[] = {
"brcm,bcm21664",
NULL,
};
DT_MACHINE_START(BCM21664_DT, "BCM21664 Broadcom Application Processor")
.init_machine = bcm21664_init,
.restart = bcm21664_restart,
.dt_compat = bcm21664_dt_compat,
MACHINE_END
arch/arm/mach-clps711x/board-autcpu12.c
View file @ ff050ad1
......@@ -265,14 +265,12 @@ static void __init autcpu12_init_late(void)
MACHINE_START(AUTCPU12, "autronix autcpu12")
/* Maintainer: Thomas Gleixner */
.atag_offset = 0x20000,
.nr_irqs = CLPS711X_NR_IRQS,
.map_io = clps711x_map_io,
.init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.init_machine = autcpu12_init,
.init_late = autcpu12_init_late,
.handle_irq = clps711x_handle_irq,
.restart = clps711x_restart,
MACHINE_END
arch/arm/mach-clps711x/board-cdb89712.c
View file @ ff050ad1
......@@ -139,12 +139,10 @@ static void __init cdb89712_init(void)
MACHINE_START(CDB89712, "Cirrus-CDB89712")
/* Maintainer: Ray Lehtiniemi */
.atag_offset = 0x100,
.nr_irqs = CLPS711X_NR_IRQS,
.map_io = clps711x_map_io,
.init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.init_machine = cdb89712_init,
.handle_irq = clps711x_handle_irq,
.restart = clps711x_restart,
MACHINE_END
arch/arm/mach-clps711x/board-clep7312.c
View file @ ff050ad1
......@@ -36,12 +36,10 @@ fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi)
MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
/* Maintainer: Nobody */
.atag_offset = 0x0100,
.nr_irqs = CLPS711X_NR_IRQS,
.fixup = fixup_clep7312,
.map_io = clps711x_map_io,
.init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.handle_irq = clps711x_handle_irq,
.restart = clps711x_restart,
MACHINE_END
arch/arm/mach-clps711x/board-edb7211.c
View file @ ff050ad1
......@@ -177,7 +177,6 @@ static void __init edb7211_init_late(void)
MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
/* Maintainer: Jon McClintock */
.atag_offset = VIDEORAM_SIZE + 0x100,
.nr_irqs = CLPS711X_NR_IRQS,
.fixup = fixup_edb7211,
.reserve = edb7211_reserve,
.map_io = clps711x_map_io,
......@@ -186,6 +185,5 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
.init_time = clps711x_timer_init,
.init_machine = edb7211_init,
.init_late = edb7211_init_late,
.handle_irq = clps711x_handle_irq,
.restart = clps711x_restart,
MACHINE_END
arch/arm/mach-clps711x/board-p720t.c
View file @ ff050ad1
......@@ -363,7 +363,6 @@ static void __init p720t_init_late(void)
MACHINE_START(P720T, "ARM-Prospector720T")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.atag_offset = 0x100,
.nr_irqs = CLPS711X_NR_IRQS,
.fixup = fixup_p720t,
.map_io = clps711x_map_io,
.init_early = clps711x_init_early,
......@@ -371,6 +370,5 @@ MACHINE_START(P720T, "ARM-Prospector720T")
.init_time = clps711x_timer_init,
.init_machine = p720t_init,
.init_late = p720t_init_late,
.handle_irq = clps711x_handle_irq,
.restart = clps711x_restart,
MACHINE_END
arch/arm/mach-clps711x/common.c
View file @ ff050ad1
......@@ -31,14 +31,14 @@
#include <linux/clk-provider.h>
#include <linux/sched_clock.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include "common.h"
static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
*clk_tint, *clk_spi;
......@@ -59,204 +59,9 @@ void __init clps711x_map_io(void)
iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
}
static void int1_mask(struct irq_data *d)
{
u32 intmr1;
intmr1 = clps_readl(INTMR1);
intmr1 &= ~(1 << d->irq);
clps_writel(intmr1, INTMR1);
}
static void int1_eoi(struct irq_data *d)
{
switch (d->irq) {
case IRQ_CSINT: clps_writel(0, COEOI); break;
case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
case IRQ_TINT: clps_writel(0, TEOI); break;
case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
}
}
static void int1_unmask(struct irq_data *d)
{
u32 intmr1;
intmr1 = clps_readl(INTMR1);
intmr1 |= 1 << d->irq;
clps_writel(intmr1, INTMR1);
}
static struct irq_chip int1_chip = {
.name = "Interrupt Vector 1",
.irq_eoi = int1_eoi,
.irq_mask = int1_mask,
.irq_unmask = int1_unmask,
};
static void int2_mask(struct irq_data *d)
{
u32 intmr2;
intmr2 = clps_readl(INTMR2);
intmr2 &= ~(1 << (d->irq - 16));
clps_writel(intmr2, INTMR2);
}
static void int2_eoi(struct irq_data *d)
{
switch (d->irq) {
case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
}
}
static void int2_unmask(struct irq_data *d)
{
u32 intmr2;
intmr2 = clps_readl(INTMR2);
intmr2 |= 1 << (d->irq - 16);
clps_writel(intmr2, INTMR2);
}
static struct irq_chip int2_chip = {
.name = "Interrupt Vector 2",
.irq_eoi = int2_eoi,
.irq_mask = int2_mask,
.irq_unmask = int2_unmask,
};
static void int3_mask(struct irq_data *d)
{
u32 intmr3;
intmr3 = clps_readl(INTMR3);
intmr3 &= ~(1 << (d->irq - 32));
clps_writel(intmr3, INTMR3);
}
static void int3_unmask(struct irq_data *d)
{
u32 intmr3;
intmr3 = clps_readl(INTMR3);
intmr3 |= 1 << (d->irq - 32);
clps_writel(intmr3, INTMR3);
}
static struct irq_chip int3_chip = {
.name = "Interrupt Vector 3",
.irq_mask = int3_mask,
.irq_unmask = int3_unmask,
};
static struct {
int nr;
struct irq_chip *chip;
irq_flow_handler_t handle;
} clps711x_irqdescs[] __initdata = {
{ IRQ_CSINT, &int1_chip, handle_fasteoi_irq, },
{ IRQ_EINT1, &int1_chip, handle_level_irq, },
{ IRQ_EINT2, &int1_chip, handle_level_irq, },
{ IRQ_EINT3, &int1_chip, handle_level_irq, },
{ IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, },
{ IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, },
{ IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, },
{ IRQ_TINT, &int1_chip, handle_fasteoi_irq, },
{ IRQ_UTXINT1, &int1_chip, handle_level_irq, },
{ IRQ_URXINT1, &int1_chip, handle_level_irq, },
{ IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, },
{ IRQ_SSEOTI, &int1_chip, handle_level_irq, },
{ IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, },
{ IRQ_SS2RX, &int2_chip, handle_level_irq, },
{ IRQ_SS2TX, &int2_chip, handle_level_irq, },
{ IRQ_UTXINT2, &int2_chip, handle_level_irq, },
{ IRQ_URXINT2, &int2_chip, handle_level_irq, },
};
void __init clps711x_init_irq(void)
{
unsigned int i;
/* Disable interrupts */
clps_writel(0, INTMR1);
clps_writel(0, INTMR2);
clps_writel(0, INTMR3);
/* Clear down any pending interrupts */
clps_writel(0, BLEOI);
clps_writel(0, MCEOI);
clps_writel(0, COEOI);
clps_writel(0, TC1EOI);
clps_writel(0, TC2EOI);
clps_writel(0, RTCEOI);
clps_writel(0, TEOI);
clps_writel(0, UMSEOI);
clps_writel(0, KBDEOI);
clps_writel(0, SRXEOF);
clps_writel(0xffffffff, DAISR);
for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
clps711x_irqdescs[i].chip,
clps711x_irqdescs[i].handle);
set_irq_flags(clps711x_irqdescs[i].nr,
IRQF_VALID | IRQF_PROBE);
}
if (IS_ENABLED(CONFIG_FIQ)) {
init_FIQ(0);
irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip,
handle_bad_irq);
set_irq_flags(IRQ_DAIINT,
IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
}
}
static inline u32 fls16(u32 x)
{
u32 r = 15;
if (!(x & 0xff00)) {
x <<= 8;
r -= 8;
}
if (!(x & 0xf000)) {
x <<= 4;
r -= 4;
}
if (!(x & 0xc000)) {
x <<= 2;
r -= 2;
}
if (!(x & 0x8000))
r--;
return r;
}
asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
{
do {
u32 irqstat;
void __iomem *base = CLPS711X_VIRT_BASE;
irqstat = readw_relaxed(base + INTSR1) &
readw_relaxed(base + INTMR1);
if (irqstat)
handle_IRQ(fls16(irqstat), regs);
irqstat = readw_relaxed(base + INTSR2) &
readw_relaxed(base + INTMR2);
if (irqstat) {
handle_IRQ(fls16(irqstat) + 16, regs);
continue;
}
break;
} while (1);
clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);
}
static u64 notrace clps711x_sched_clock_read(void)
......
arch/arm/mach-clps711x/common.h
View file @ ff050ad1
......@@ -6,13 +6,14 @@
#include <linux/reboot.h>
#define CLPS711X_NR_IRQS (33)
#define CLPS711X_NR_GPIO (4 * 8 + 3)
#define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
extern void clps711x_map_io(void);
extern void clps711x_init_irq(void);
extern void clps711x_timer_init(void);
extern void clps711x_handle_irq(struct pt_regs *regs);
extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
extern void clps711x_init_early(void);
/* drivers/irqchip/irq-clps711x.c */
void clps711x_intc_init(phys_addr_t, resource_size_t);
arch/arm/mach-clps711x/include/mach/clps711x.h
View file @ ff050ad1
......@@ -40,8 +40,6 @@
#define MEMCFG1 (0x0180)
#define MEMCFG2 (0x01c0)
#define DRFPR (0x0200)
#define INTSR1 (0x0240)
#define INTMR1 (0x0280)
#define LCDCON (0x02c0)
#define TC1D (0x0300)
#define TC2D (0x0340)
......@@ -55,28 +53,16 @@
#define PALLSW (0x0540)
#define PALMSW (0x0580)
#define STFCLR (0x05c0)
#define BLEOI (0x0600)
#define MCEOI (0x0640)
#define TEOI (0x0680)
#define TC1EOI (0x06c0)
#define TC2EOI (0x0700)
#define RTCEOI (0x0740)
#define UMSEOI (0x0780)
#define COEOI (0x07c0)
#define HALT (0x0800)
#define STDBY (0x0840)
#define FBADDR (0x1000)
#define SYSCON2 (0x1100)
#define SYSFLG2 (0x1140)
#define INTSR2 (0x1240)
#define INTMR2 (0x1280)
#define UARTDR2 (0x1480)
#define UBRLCR2 (0x14c0)
#define SS2DR (0x1500)
#define SRXEOF (0x1600)
#define SS2POP (0x16c0)
#define KBDEOI (0x1700)
#define DAIR (0x2000)
#define DAIDR0 (0x2040)
......@@ -84,8 +70,6 @@
#define DAIDR2 (0x20c0)
#define DAISR (0x2100)
#define SYSCON3 (0x2200)
#define INTSR3 (0x2240)
#define INTMR3 (0x2280)
#define LEDFLSH (0x22c0)
#define SDCONF (0x2300)
#define SDRFPR (0x2340)
......
arch/arm/mach-davinci/Kconfig
View file @ ff050ad1
......@@ -51,11 +51,6 @@ config ARCH_DAVINCI_DM365
select AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_TNETV107X
bool "TNETV107X based system"
select CPU_V6
select CP_INTC
comment "DaVinci Board Type"
config MACH_DA8XX_DT
......@@ -215,13 +210,6 @@ config DA850_WL12XX
AM18x EVM.
config MACH_TNETV107X
bool "TI TNETV107X Reference Platform"
default ARCH_DAVINCI_TNETV107X
depends on ARCH_DAVINCI_TNETV107X
help
Say Y here to select the TI TNETV107X Evaluation Module.
config MACH_MITYOMAPL138
bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
depends on ARCH_DAVINCI_DA850
......
arch/arm/mach-davinci/Makefile
View file @ ff050ad1
......@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o
obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += tnetv107x.o devices-tnetv107x.o
obj-$(CONFIG_AINTC) += irq.o
obj-$(CONFIG_CP_INTC) += cp_intc.o
......@@ -32,7 +31,6 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o
obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o
obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o
obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o
......
arch/arm/mach-davinci/Makefile.boot
View file @ ff050ad1
ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y)
ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
$(error Cannot enable DaVinci and DA8XX platforms concurrently)
else
zreladdr-y += 0xc0008000
params_phys-y := 0xc0000100
initrd_phys-y := 0xc0800000
endif
else
zreladdr-y += 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000
endif
zreladdr-$(CONFIG_ARCH_DAVINCI_DA8XX) += 0xc0008000
params_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0000100
initrd_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0800000
zreladdr-$(CONFIG_ARCH_DAVINCI_DMx) += 0x80008000
params_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80000100
initrd_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80800000
arch/arm/mach-davinci/board-tnetv107x-evm.c deleted 100644 → 0
View file @ dfc25e45
/*
* Texas Instruments TNETV107X EVM Board Support
*
* Copyright (C) 2010 Texas Instruments
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/ratelimit.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <linux/platform_data/edma.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/irqs.h>
#include <mach/mux.h>
#include <mach/cp_intc.h>
#include <mach/tnetv107x.h>
#define EVM_MMC_WP_GPIO 21
#define EVM_MMC_CD_GPIO 24
#define EVM_SPI_CS_GPIO 54
static int initialize_gpio(int gpio, char *desc)
{
int ret;
ret = gpio_request(gpio, desc);
if (ret < 0) {
pr_err_ratelimited("cannot open %s gpio\n", desc);
return -ENOSYS;
}
gpio_direction_input(gpio);
return gpio;
}
static int mmc_get_cd(int index)
{
static int gpio;
if (!gpio)
gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
if (gpio < 0)
return gpio;
return gpio_get_value(gpio) ? 0 : 1;
}
static int mmc_get_ro(int index)
{
static int gpio;
if (!gpio)
gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
if (gpio < 0)
return gpio;
return gpio_get_value(gpio) ? 1 : 0;
}
static struct davinci_mmc_config mmc_config = {
.get_cd = mmc_get_cd,
.get_ro = mmc_get_ro,
.wires = 4,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
};
static const short sdio1_pins[] __initconst = {
TNETV107X_SDIO1_CLK_1, TNETV107X_SDIO1_CMD_1,
TNETV107X_SDIO1_DATA0_1, TNETV107X_SDIO1_DATA1_1,
TNETV107X_SDIO1_DATA2_1, TNETV107X_SDIO1_DATA3_1,
TNETV107X_GPIO21, TNETV107X_GPIO24,
-1
};
static const short uart1_pins[] __initconst = {
TNETV107X_UART1_RD, TNETV107X_UART1_TD,
-1
};
static const short ssp_pins[] __initconst = {
TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
TNETV107X_SSP1_3, -1
};
static struct mtd_partition nand_partitions[] = {
/* bootloader (U-Boot, etc) in first 12 sectors */
{
.name = "bootloader",
.offset = 0,
.size = (12*SZ_128K),
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* bootloader params in the next sector */
{
.name = "params",
.offset = MTDPART_OFS_NXTBLK,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* kernel */
{
.name = "kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = SZ_4M,
.mask_flags = 0,
},
/* file system */
{
.name = "filesystem",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0,
}
};
static struct davinci_nand_pdata nand_config = {
.mask_cle = 0x4000,
.mask_ale = 0x2000,
.parts = nand_partitions,
.nr_parts = ARRAY_SIZE(nand_partitions),
.ecc_mode = NAND_ECC_HW,
.bbt_options = NAND_BBT_USE_FLASH,
.ecc_bits = 1,
};
static struct davinci_uart_config serial_config __initconst = {
.enabled_uarts = BIT(1),
};
static const uint32_t keymap[] = {
KEY(0, 0, KEY_NUMERIC_1),
KEY(0, 1, KEY_NUMERIC_2),
KEY(0, 2, KEY_NUMERIC_3),
KEY(0, 3, KEY_FN_F1),
KEY(0, 4, KEY_MENU),
KEY(1, 0, KEY_NUMERIC_4),
KEY(1, 1, KEY_NUMERIC_5),
KEY(1, 2, KEY_NUMERIC_6),
KEY(1, 3, KEY_UP),
KEY(1, 4, KEY_FN_F2),
KEY(2, 0, KEY_NUMERIC_7),
KEY(2, 1, KEY_NUMERIC_8),
KEY(2, 2, KEY_NUMERIC_9),
KEY(2, 3, KEY_LEFT),
KEY(2, 4, KEY_ENTER),
KEY(3, 0, KEY_NUMERIC_STAR),
KEY(3, 1, KEY_NUMERIC_0),
KEY(3, 2, KEY_NUMERIC_POUND),
KEY(3, 3, KEY_DOWN),
KEY(3, 4, KEY_RIGHT),
KEY(4, 0, KEY_FN_F3),
KEY(4, 1, KEY_FN_F4),
KEY(4, 2, KEY_MUTE),
KEY(4, 3, KEY_HOME),
KEY(4, 4, KEY_BACK),
KEY(5, 0, KEY_VOLUMEDOWN),
KEY(5, 1, KEY_VOLUMEUP),
KEY(5, 2, KEY_F1),
KEY(5, 3, KEY_F2),
KEY(5, 4, KEY_F3),
};
static const struct matrix_keymap_data keymap_data = {
.keymap = keymap,
.keymap_size = ARRAY_SIZE(keymap),
};
static struct matrix_keypad_platform_data keypad_config = {
.keymap_data = &keymap_data,
.num_row_gpios = 6,
.num_col_gpios = 5,
.debounce_ms = 0, /* minimum */
.active_low = 0, /* pull up realization */
.no_autorepeat = 0,
};
static void spi_select_device(int cs)
{
static int gpio;
if (!gpio) {
int ret;
ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
if (ret < 0) {
pr_err("cannot open spi chipsel gpio\n");
gpio = -ENOSYS;
return;
} else {
gpio = EVM_SPI_CS_GPIO;
gpio_direction_output(gpio, 0);
}
}
if (gpio < 0)
return;
return gpio_set_value(gpio, cs ? 1 : 0);
}
static struct ti_ssp_spi_data spi_master_data = {
.num_cs = 2,
.select = spi_select_device,
.iosel = SSP_PIN_SEL(0, SSP_CLOCK) | SSP_PIN_SEL(1, SSP_DATA) |
SSP_PIN_SEL(2, SSP_CHIPSEL) | SSP_PIN_SEL(3, SSP_IN) |
SSP_INPUT_SEL(3),
};
static struct ti_ssp_data ssp_config = {
.out_clock = 250 * 1000,
.dev_data = {
[1] = {
.dev_name = "ti-ssp-spi",
.pdata = &spi_master_data,
.pdata_size = sizeof(spi_master_data),
},
},
};
static struct tnetv107x_device_info evm_device_info __initconst = {
.serial_config = &serial_config,
.mmc_config[1] = &mmc_config, /* controller 1 */
.nand_config[0] = &nand_config, /* chip select 0 */
.keypad_config = &keypad_config,
.ssp_config = &ssp_config,
};
static struct spi_board_info spi_info[] __initconst = {
};
static __init void tnetv107x_evm_board_init(void)
{
davinci_cfg_reg_list(sdio1_pins);
davinci_cfg_reg_list(uart1_pins);
davinci_cfg_reg_list(ssp_pins);
tnetv107x_devices_init(&evm_device_info);
spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init tnetv107x_evm_console_init(void)
{
return add_preferred_console("ttyS", 0, "115200");
}
console_initcall(tnetv107x_evm_console_init);
#endif
MACHINE_START(TNETV107X, "TNETV107X EVM")
.atag_offset = 0x100,
.map_io = tnetv107x_init,
.init_irq = cp_intc_init,
.init_time = davinci_timer_init,
.init_machine = tnetv107x_evm_board_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = tnetv107x_restart,
MACHINE_END
arch/arm/mach-davinci/davinci.h
View file @ ff050ad1
......@@ -79,6 +79,8 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata);
#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
int davinci_init_wdt(void);
/* DM355 function declarations */
void dm355_init(void);
void dm355_init_spi0(unsigned chipselect_mask,
......
arch/arm/mach-davinci/devices-tnetv107x.c deleted 100644 → 0
View file @ dfc25e45
This diff is collapsed.
arch/arm/mach-davinci/devices.c
View file @ ff050ad1
......@@ -313,9 +313,9 @@ void davinci_restart(enum reboot_mode mode, const char *cmd)
davinci_watchdog_reset(&davinci_wdt_device);
}
static void davinci_init_wdt(void)
int davinci_init_wdt(void)
{
platform_device_register(&davinci_wdt_device);
return platform_device_register(&davinci_wdt_device);
}
static struct platform_device davinci_gpio_device = {
......@@ -348,16 +348,3 @@ struct davinci_timer_instance davinci_timer_instance[2] = {
},
};
/*-------------------------------------------------------------------------*/
static int __init davinci_init_devices(void)
{
/* please keep these calls, and their implementations above,
* in alphabetical order so they're easier to sort through.
*/
davinci_init_wdt();
return 0;
}
arch_initcall(davinci_init_devices);
arch/arm/mach-davinci/dm355.c
View file @ ff050ad1
......@@ -1076,12 +1076,18 @@ int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
static int __init dm355_init_devices(void)
{
int ret = 0;
if (!cpu_is_davinci_dm355())
return 0;
davinci_cfg_reg(DM355_INT_EDMA_CC);
platform_device_register(&dm355_edma_device);
return 0;
ret = davinci_init_wdt();
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
return ret;
}
postcore_initcall(dm355_init_devices);
arch/arm/mach-davinci/dm365.c
View file @ ff050ad1
......@@ -1436,6 +1436,8 @@ int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
static int __init dm365_init_devices(void)
{
int ret = 0;
if (!cpu_is_davinci_dm365())
return 0;
......@@ -1445,6 +1447,10 @@ static int __init dm365_init_devices(void)
platform_device_register(&dm365_mdio_device);
platform_device_register(&dm365_emac_device);
return 0;
ret = davinci_init_wdt();
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
return ret;
}
postcore_initcall(dm365_init_devices);
arch/arm/mach-davinci/dm644x.c
View file @ ff050ad1
......@@ -964,6 +964,8 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
static int __init dm644x_init_devices(void)
{
int ret = 0;
if (!cpu_is_davinci_dm644x())
return 0;
......@@ -972,6 +974,10 @@ static int __init dm644x_init_devices(void)
platform_device_register(&dm644x_mdio_device);
platform_device_register(&dm644x_emac_device);
return 0;
ret = davinci_init_wdt();
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
return ret;
}
postcore_initcall(dm644x_init_devices);
arch/arm/mach-davinci/dm646x.c
View file @ ff050ad1
......@@ -955,12 +955,18 @@ void __init dm646x_init(void)
static int __init dm646x_init_devices(void)
{
int ret = 0;
if (!cpu_is_davinci_dm646x())
return 0;
platform_device_register(&dm646x_mdio_device);
platform_device_register(&dm646x_emac_device);
return 0;
ret = davinci_init_wdt();
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
return ret;
}
postcore_initcall(dm646x_init_devices);
arch/arm/mach-davinci/include/mach/cputype.h
View file @ ff050ad1
......@@ -33,7 +33,6 @@ struct davinci_id {
#define DAVINCI_CPU_ID_DM365 0x03650000
#define DAVINCI_CPU_ID_DA830 0x08300000
#define DAVINCI_CPU_ID_DA850 0x08500000
#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000
#define IS_DAVINCI_CPU(type, id) \
static inline int is_davinci_ ##type(void) \
......@@ -47,7 +46,6 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
#ifdef CONFIG_ARCH_DAVINCI_DM644x
#define cpu_is_davinci_dm644x() is_davinci_dm644x()
......@@ -85,10 +83,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
#define cpu_is_davinci_da850() 0
#endif
#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
#else
#define cpu_is_davinci_tnetv107x() 0
#endif
#endif
arch/arm/mach-davinci/include/mach/irqs.h
View file @ ff050ad1
......@@ -401,103 +401,6 @@
#define DA850_N_CP_INTC_IRQ 101
/* TNETV107X specific interrupts */
#define IRQ_TNETV107X_TDM1_TXDMA 0
#define IRQ_TNETV107X_EXT_INT_0 1
#define IRQ_TNETV107X_EXT_INT_1 2
#define IRQ_TNETV107X_GPIO_INT12 3
#define IRQ_TNETV107X_GPIO_INT13 4
#define IRQ_TNETV107X_TIMER_0_TINT12 5
#define IRQ_TNETV107X_TIMER_1_TINT12 6
#define IRQ_TNETV107X_UART0 7
#define IRQ_TNETV107X_TDM1_RXDMA 8
#define IRQ_TNETV107X_MCDMA_INT0 9
#define IRQ_TNETV107X_MCDMA_INT1 10
#define IRQ_TNETV107X_TPCC 11
#define IRQ_TNETV107X_TPCC_INT0 12
#define IRQ_TNETV107X_TPCC_INT1 13
#define IRQ_TNETV107X_TPCC_INT2 14
#define IRQ_TNETV107X_TPCC_INT3 15
#define IRQ_TNETV107X_TPTC0 16
#define IRQ_TNETV107X_TPTC1 17
#define IRQ_TNETV107X_TIMER_0_TINT34 18
#define IRQ_TNETV107X_ETHSS 19
#define IRQ_TNETV107X_TIMER_1_TINT34 20
#define IRQ_TNETV107X_DSP2ARM_INT0 21
#define IRQ_TNETV107X_DSP2ARM_INT1 22
#define IRQ_TNETV107X_ARM_NPMUIRQ 23
#define IRQ_TNETV107X_USB1 24
#define IRQ_TNETV107X_VLYNQ 25
#define IRQ_TNETV107X_UART0_DMATX 26
#define IRQ_TNETV107X_UART0_DMARX 27
#define IRQ_TNETV107X_TDM1_TXMCSP 28
#define IRQ_TNETV107X_SSP 29
#define IRQ_TNETV107X_MCDMA_INT2 30
#define IRQ_TNETV107X_MCDMA_INT3 31
#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
#define IRQ_TNETV107X_USB0 34
#define IRQ_TNETV107X_USB_CDMA 35
#define IRQ_TNETV107X_LCD 36
#define IRQ_TNETV107X_KEYPAD 37
#define IRQ_TNETV107X_KEYPAD_FREE 38
#define IRQ_TNETV107X_RNG 39
#define IRQ_TNETV107X_PKA 40
#define IRQ_TNETV107X_TDM0_TXDMA 41
#define IRQ_TNETV107X_TDM0_RXDMA 42
#define IRQ_TNETV107X_TDM0_TXMCSP 43
#define IRQ_TNETV107X_TDM0_RXMCSP 44
#define IRQ_TNETV107X_TDM1_RXMCSP 45
#define IRQ_TNETV107X_SDIO1 46
#define IRQ_TNETV107X_SDIO0 47
#define IRQ_TNETV107X_TSC 48
#define IRQ_TNETV107X_TS 49
#define IRQ_TNETV107X_UART1 50
#define IRQ_TNETV107X_MBX_LITE 51
#define IRQ_TNETV107X_GPIO_INT00 52
#define IRQ_TNETV107X_GPIO_INT01 53
#define IRQ_TNETV107X_GPIO_INT02 54
#define IRQ_TNETV107X_GPIO_INT03 55
#define IRQ_TNETV107X_UART2 56
#define IRQ_TNETV107X_UART2_DMATX 57
#define IRQ_TNETV107X_UART2_DMARX 58
#define IRQ_TNETV107X_IMCOP_IMX 59
#define IRQ_TNETV107X_IMCOP_VLCD 60
#define IRQ_TNETV107X_AES 61
#define IRQ_TNETV107X_DES 62
#define IRQ_TNETV107X_SHAMD5 63
#define IRQ_TNETV107X_TPCC_ERR 68
#define IRQ_TNETV107X_TPCC_PROT 69
#define IRQ_TNETV107X_TPTC0_ERR 70
#define IRQ_TNETV107X_TPTC1_ERR 71
#define IRQ_TNETV107X_UART0_ERR 72
#define IRQ_TNETV107X_UART1_ERR 73
#define IRQ_TNETV107X_AEMIF_ERR 74
#define IRQ_TNETV107X_DDR_ERR 75
#define IRQ_TNETV107X_WDTARM_INT0 76
#define IRQ_TNETV107X_MCDMA_ERR 77
#define IRQ_TNETV107X_GPIO_ERR 78
#define IRQ_TNETV107X_MPU_ADDR 79
#define IRQ_TNETV107X_MPU_PROT 80
#define IRQ_TNETV107X_IOPU_ADDR 81
#define IRQ_TNETV107X_IOPU_PROT 82
#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
#define IRQ_TNETV107X_PLL_UNLOCK 87
#define IRQ_TNETV107X_WDTDSP_INT0 88
#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
#define IRQ_TNETV107X_PBIST_CPU 91
#define IRQ_TNETV107X_WDTARM 92
#define IRQ_TNETV107X_PSC 93
#define IRQ_TNETV107X_MMC0 94
#define IRQ_TNETV107X_MMC1 95
#define TNETV107X_N_CP_INTC_IRQ 96
/* da850 currently has the most gpio pins (144) */
#define DAVINCI_N_GPIO 144
/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
......
arch/arm/mach-davinci/include/mach/mux.h
View file @ ff050ad1
......@@ -972,275 +972,6 @@ enum davinci_da850_index {
DA850_VPIF_CLKO3,
};
enum davinci_tnetv107x_index {
TNETV107X_ASR_A00,
TNETV107X_GPIO32,
TNETV107X_ASR_A01,
TNETV107X_GPIO33,
TNETV107X_ASR_A02,
TNETV107X_GPIO34,
TNETV107X_ASR_A03,
TNETV107X_GPIO35,
TNETV107X_ASR_A04,
TNETV107X_GPIO36,
TNETV107X_ASR_A05,
TNETV107X_GPIO37,
TNETV107X_ASR_A06,
TNETV107X_GPIO38,
TNETV107X_ASR_A07,
TNETV107X_GPIO39,
TNETV107X_ASR_A08,
TNETV107X_GPIO40,
TNETV107X_ASR_A09,
TNETV107X_GPIO41,
TNETV107X_ASR_A10,
TNETV107X_GPIO42,
TNETV107X_ASR_A11,
TNETV107X_BOOT_STRP_0,
TNETV107X_ASR_A12,
TNETV107X_BOOT_STRP_1,
TNETV107X_ASR_A13,
TNETV107X_GPIO43,
TNETV107X_ASR_A14,
TNETV107X_GPIO44,
TNETV107X_ASR_A15,
TNETV107X_GPIO45,
TNETV107X_ASR_A16,
TNETV107X_GPIO46,
TNETV107X_ASR_A17,
TNETV107X_GPIO47,
TNETV107X_ASR_A18,
TNETV107X_GPIO48,
TNETV107X_SDIO1_DATA3_0,
TNETV107X_ASR_A19,
TNETV107X_GPIO49,
TNETV107X_SDIO1_DATA2_0,
TNETV107X_ASR_A20,
TNETV107X_GPIO50,
TNETV107X_SDIO1_DATA1_0,
TNETV107X_ASR_A21,
TNETV107X_GPIO51,
TNETV107X_SDIO1_DATA0_0,
TNETV107X_ASR_A22,
TNETV107X_GPIO52,
TNETV107X_SDIO1_CMD_0,
TNETV107X_ASR_A23,
TNETV107X_GPIO53,
TNETV107X_SDIO1_CLK_0,
TNETV107X_ASR_BA_1,
TNETV107X_GPIO54,
TNETV107X_SYS_PLL_CLK,
TNETV107X_ASR_CS0,
TNETV107X_ASR_CS1,
TNETV107X_ASR_CS2,
TNETV107X_TDM_PLL_CLK,
TNETV107X_ASR_CS3,
TNETV107X_ETH_PHY_CLK,
TNETV107X_ASR_D00,
TNETV107X_GPIO55,
TNETV107X_ASR_D01,
TNETV107X_GPIO56,
TNETV107X_ASR_D02,
TNETV107X_GPIO57,
TNETV107X_ASR_D03,
TNETV107X_GPIO58,
TNETV107X_ASR_D04,
TNETV107X_GPIO59_0,
TNETV107X_ASR_D05,
TNETV107X_GPIO60_0,
TNETV107X_ASR_D06,
TNETV107X_GPIO61_0,
TNETV107X_ASR_D07,
TNETV107X_GPIO62_0,
TNETV107X_ASR_D08,
TNETV107X_GPIO63_0,
TNETV107X_ASR_D09,
TNETV107X_GPIO64_0,
TNETV107X_ASR_D10,
TNETV107X_SDIO1_DATA3_1,
TNETV107X_ASR_D11,
TNETV107X_SDIO1_DATA2_1,
TNETV107X_ASR_D12,
TNETV107X_SDIO1_DATA1_1,
TNETV107X_ASR_D13,
TNETV107X_SDIO1_DATA0_1,
TNETV107X_ASR_D14,
TNETV107X_SDIO1_CMD_1,
TNETV107X_ASR_D15,
TNETV107X_SDIO1_CLK_1,
TNETV107X_ASR_OE,
TNETV107X_BOOT_STRP_2,
TNETV107X_ASR_RNW,
TNETV107X_GPIO29_0,
TNETV107X_ASR_WAIT,
TNETV107X_GPIO30_0,
TNETV107X_ASR_WE,
TNETV107X_BOOT_STRP_3,
TNETV107X_ASR_WE_DQM0,
TNETV107X_GPIO31,
TNETV107X_LCD_PD17_0,
TNETV107X_ASR_WE_DQM1,
TNETV107X_ASR_BA0_0,
TNETV107X_VLYNQ_CLK,
TNETV107X_GPIO14,
TNETV107X_LCD_PD19_0,
TNETV107X_VLYNQ_RXD0,
TNETV107X_GPIO15,
TNETV107X_LCD_PD20_0,
TNETV107X_VLYNQ_RXD1,
TNETV107X_GPIO16,
TNETV107X_LCD_PD21_0,
TNETV107X_VLYNQ_TXD0,
TNETV107X_GPIO17,
TNETV107X_LCD_PD22_0,
TNETV107X_VLYNQ_TXD1,
TNETV107X_GPIO18,
TNETV107X_LCD_PD23_0,
TNETV107X_SDIO0_CLK,
TNETV107X_GPIO19,
TNETV107X_SDIO0_CMD,
TNETV107X_GPIO20,
TNETV107X_SDIO0_DATA0,
TNETV107X_GPIO21,
TNETV107X_SDIO0_DATA1,
TNETV107X_GPIO22,
TNETV107X_SDIO0_DATA2,
TNETV107X_GPIO23,
TNETV107X_SDIO0_DATA3,
TNETV107X_GPIO24,
TNETV107X_EMU0,
TNETV107X_EMU1,
TNETV107X_RTCK,
TNETV107X_TRST_N,
TNETV107X_TCK,
TNETV107X_TDI,
TNETV107X_TDO,
TNETV107X_TMS,
TNETV107X_TDM1_CLK,
TNETV107X_TDM1_RX,
TNETV107X_TDM1_TX,
TNETV107X_TDM1_FS,
TNETV107X_KEYPAD_R0,
TNETV107X_KEYPAD_R1,
TNETV107X_KEYPAD_R2,
TNETV107X_KEYPAD_R3,
TNETV107X_KEYPAD_R4,
TNETV107X_KEYPAD_R5,
TNETV107X_KEYPAD_R6,
TNETV107X_GPIO12,
TNETV107X_KEYPAD_R7,
TNETV107X_GPIO10,
TNETV107X_KEYPAD_C0,
TNETV107X_KEYPAD_C1,
TNETV107X_KEYPAD_C2,
TNETV107X_KEYPAD_C3,
TNETV107X_KEYPAD_C4,
TNETV107X_KEYPAD_C5,
TNETV107X_KEYPAD_C6,
TNETV107X_GPIO13,
TNETV107X_TEST_CLK_IN,
TNETV107X_KEYPAD_C7,
TNETV107X_GPIO11,
TNETV107X_SSP0_0,
TNETV107X_SCC_DCLK,
TNETV107X_LCD_PD20_1,
TNETV107X_SSP0_1,
TNETV107X_SCC_CS_N,
TNETV107X_LCD_PD21_1,
TNETV107X_SSP0_2,
TNETV107X_SCC_D,
TNETV107X_LCD_PD22_1,
TNETV107X_SSP0_3,
TNETV107X_SCC_RESETN,
TNETV107X_LCD_PD23_1,
TNETV107X_SSP1_0,
TNETV107X_GPIO25,
TNETV107X_UART2_CTS,
TNETV107X_SSP1_1,
TNETV107X_GPIO26,
TNETV107X_UART2_RD,
TNETV107X_SSP1_2,
TNETV107X_GPIO27,
TNETV107X_UART2_RTS,
TNETV107X_SSP1_3,
TNETV107X_GPIO28,
TNETV107X_UART2_TD,
TNETV107X_UART0_CTS,
TNETV107X_UART0_RD,
TNETV107X_UART0_RTS,
TNETV107X_UART0_TD,
TNETV107X_UART1_RD,
TNETV107X_UART1_TD,
TNETV107X_LCD_AC_NCS,
TNETV107X_LCD_HSYNC_RNW,
TNETV107X_LCD_VSYNC_A0,
TNETV107X_LCD_MCLK,
TNETV107X_LCD_PD16_0,
TNETV107X_LCD_PCLK_E,
TNETV107X_LCD_PD00,
TNETV107X_LCD_PD01,
TNETV107X_LCD_PD02,
TNETV107X_LCD_PD03,
TNETV107X_LCD_PD04,
TNETV107X_LCD_PD05,
TNETV107X_LCD_PD06,
TNETV107X_LCD_PD07,
TNETV107X_LCD_PD08,
TNETV107X_GPIO59_1,
TNETV107X_LCD_PD09,
TNETV107X_GPIO60_1,
TNETV107X_LCD_PD10,
TNETV107X_ASR_BA0_1,
TNETV107X_GPIO61_1,
TNETV107X_LCD_PD11,
TNETV107X_GPIO62_1,
TNETV107X_LCD_PD12,
TNETV107X_GPIO63_1,
TNETV107X_LCD_PD13,
TNETV107X_GPIO64_1,
TNETV107X_LCD_PD14,
TNETV107X_GPIO29_1,
TNETV107X_LCD_PD15,
TNETV107X_GPIO30_1,
TNETV107X_EINT0,
TNETV107X_GPIO08,
TNETV107X_EINT1,
TNETV107X_GPIO09,
TNETV107X_GPIO00,
TNETV107X_LCD_PD20_2,
TNETV107X_TDM_CLK_IN_2,
TNETV107X_GPIO01,
TNETV107X_LCD_PD21_2,
TNETV107X_24M_CLK_OUT_1,
TNETV107X_GPIO02,
TNETV107X_LCD_PD22_2,
TNETV107X_GPIO03,
TNETV107X_LCD_PD23_2,
TNETV107X_GPIO04,
TNETV107X_LCD_PD16_1,
TNETV107X_USB0_RXERR,
TNETV107X_GPIO05,
TNETV107X_LCD_PD17_1,
TNETV107X_TDM_CLK_IN_1,
TNETV107X_GPIO06,
TNETV107X_LCD_PD18,
TNETV107X_24M_CLK_OUT_2,
TNETV107X_GPIO07,
TNETV107X_LCD_PD19_1,
TNETV107X_USB1_RXERR,
TNETV107X_ETH_PLL_CLK,
TNETV107X_MDIO,
TNETV107X_MDC,
TNETV107X_AIC_MUTE_STAT_N,
TNETV107X_TDM0_CLK,
TNETV107X_AIC_HNS_EN_N,
TNETV107X_TDM0_FS,
TNETV107X_AIC_HDS_EN_STAT_N,
TNETV107X_TDM0_TX,
TNETV107X_AIC_HNF_EN_STAT_N,
TNETV107X_TDM0_RX,
};
#define PINMUX(x) (4 * (x))
#ifdef CONFIG_DAVINCI_MUX
......
arch/arm/mach-davinci/include/mach/psc.h
View file @ ff050ad1
......@@ -182,53 +182,6 @@
#define DA8XX_LPSC1_CR_P3_SS 26
#define DA8XX_LPSC1_L3_CBA_RAM 31
/* TNETV107X LPSC Assignments */
#define TNETV107X_LPSC_ARM 0
#define TNETV107X_LPSC_GEM 1
#define TNETV107X_LPSC_DDR2_PHY 2
#define TNETV107X_LPSC_TPCC 3
#define TNETV107X_LPSC_TPTC0 4
#define TNETV107X_LPSC_TPTC1 5
#define TNETV107X_LPSC_RAM 6
#define TNETV107X_LPSC_MBX_LITE 7
#define TNETV107X_LPSC_LCD 8
#define TNETV107X_LPSC_ETHSS 9
#define TNETV107X_LPSC_AEMIF 10
#define TNETV107X_LPSC_CHIP_CFG 11
#define TNETV107X_LPSC_TSC 12
#define TNETV107X_LPSC_ROM 13
#define TNETV107X_LPSC_UART2 14
#define TNETV107X_LPSC_PKTSEC 15
#define TNETV107X_LPSC_SECCTL 16
#define TNETV107X_LPSC_KEYMGR 17
#define TNETV107X_LPSC_KEYPAD 18
#define TNETV107X_LPSC_GPIO 19
#define TNETV107X_LPSC_MDIO 20
#define TNETV107X_LPSC_SDIO0 21
#define TNETV107X_LPSC_UART0 22
#define TNETV107X_LPSC_UART1 23
#define TNETV107X_LPSC_TIMER0 24
#define TNETV107X_LPSC_TIMER1 25
#define TNETV107X_LPSC_WDT_ARM 26
#define TNETV107X_LPSC_WDT_DSP 27
#define TNETV107X_LPSC_SSP 28
#define TNETV107X_LPSC_TDM0 29
#define TNETV107X_LPSC_VLYNQ 30
#define TNETV107X_LPSC_MCDMA 31
#define TNETV107X_LPSC_USB0 32
#define TNETV107X_LPSC_TDM1 33
#define TNETV107X_LPSC_DEBUGSS 34
#define TNETV107X_LPSC_ETHSS_RGMII 35
#define TNETV107X_LPSC_SYSTEM 36
#define TNETV107X_LPSC_IMCOP 37
#define TNETV107X_LPSC_SPARE 38
#define TNETV107X_LPSC_SDIO1 39
#define TNETV107X_LPSC_USB1 40
#define TNETV107X_LPSC_USBSS 41
#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
#define TNETV107X_LPSC_MAX 44
/* PSC register offsets */
#define EPCPR 0x070
#define PTCMD 0x120
......
arch/arm/mach-davinci/include/mach/serial.h
View file @ ff050ad1
......@@ -23,14 +23,6 @@
#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
#define TNETV107X_UART0_BASE 0x08108100
#define TNETV107X_UART1_BASE 0x08088400
#define TNETV107X_UART2_BASE 0x08108300
#define TNETV107X_UART0_VIRT IOMEM(0xfee08100)
#define TNETV107X_UART1_VIRT IOMEM(0xfed88400)
#define TNETV107X_UART2_VIRT IOMEM(0xfee08300)
/* DaVinci UART register offsets */
#define UART_DAVINCI_PWREMU 0x0c
#define UART_DM646X_SCR 0x10
......
arch/arm/mach-davinci/include/mach/tnetv107x.h deleted 100644 → 0
View file @ dfc25e45
/*
* Texas Instruments TNETV107X SoC Specific Defines
*
* Copyright (C) 2010 Texas Instruments
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
#define __ASM_ARCH_DAVINCI_TNETV107X_H
#include <asm/sizes.h>
#define TNETV107X_DDR_BASE 0x80000000
/*
* Fixed mapping for early init starts here. If low-level debug is enabled,
* this area also gets mapped via io_pg_offset and io_phys by the boot code.
* To fit in with the io_pg_offset calculation, the io base address selected
* here _must_ be a multiple of 2^20.
*/
#define TNETV107X_IO_BASE 0x08000000
#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M)
#define TNETV107X_N_GPIO 65
#ifndef __ASSEMBLY__
#include <linux/serial_8250.h>
#include <linux/input/matrix_keypad.h>
#include <linux/mfd/ti_ssp.h>
#include <linux/reboot.h>
#include <linux/platform_data/mmc-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <mach/serial.h>
struct tnetv107x_device_info {
struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
struct matrix_keypad_platform_data *keypad_config;
struct ti_ssp_data *ssp_config;
};
extern struct platform_device tnetv107x_wdt_device;
extern struct platform_device tnetv107x_serial_device[];
extern void tnetv107x_init(void);
extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
extern void tnetv107x_irq_init(void);
void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
#endif
#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
arch/arm/mach-davinci/include/mach/uncompress.h
View file @ ff050ad1
......@@ -68,9 +68,6 @@ static inline void set_uart_info(u32 phys)
#define DEBUG_LL_DA8XX(machine, port) \
_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
#define DEBUG_LL_TNETV107X(machine, port) \
_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE)
static inline void __arch_decomp_setup(unsigned long arch_id)
{
/*
......@@ -94,9 +91,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_DA8XX(davinci_da850_evm, 2);
DEBUG_LL_DA8XX(mityomapl138, 1);
DEBUG_LL_DA8XX(omapl138_hawkboard, 2);
/* TNETV107x boards */
DEBUG_LL_TNETV107X(tnetv107x, 1);
} while (0);
}
......
arch/arm/mach-davinci/tnetv107x.c deleted 100644 → 0
View file @ dfc25e45
This diff is collapsed.
arch/arm/mach-dove/Kconfig
View file @ ff050ad1
......@@ -20,18 +20,6 @@ config MACH_CM_A510
Say 'Y' here if you want your kernel to support the
CompuLab CM-A510 Board.
config MACH_DOVE_DT
bool "Marvell Dove Flattened Device Tree"
select DOVE_CLK
select ORION_IRQCHIP
select ORION_TIMER
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
select USE_OF
help
Say 'Y' here if you want your kernel to support the
Marvell Dove using flattened device tree.
endmenu
endif
arch/arm/mach-dove/Makefile
View file @ ff050ad1
......@@ -2,5 +2,4 @@ obj-y += common.o
obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
obj-$(CONFIG_MACH_DOVE_DT) += board-dt.o
obj-$(CONFIG_MACH_CM_A510) += cm-a510.o
arch/arm/mach-imx/Kconfig
View file @ ff050ad1
config ARCH_MXC
bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
select ARCH_HAS_CPUFREQ
select ARCH_HAS_OPP
select ARCH_REQUIRE_GPIOLIB
select ARM_CPU_SUSPEND if PM
select CLKSRC_MMIO
select GENERIC_ALLOCATOR
select GENERIC_IRQ_CHIP
select PINCTRL
select PM_OPP if PM
select SOC_BUS
select SRAM
help
Support for Freescale MXC/iMX-based family of processors
......@@ -116,8 +119,8 @@ config SOC_IMX35
select ARCH_MXC_IOMUX_V3
select HAVE_EPIT
select MXC_AVIC
select PINCTRL_IMX35
select SMP_ON_UP if SMP
select PINCTRL
config SOC_IMX5
bool
......@@ -768,53 +771,43 @@ config SOC_IMX50
config SOC_IMX53
bool "i.MX53 support"
select HAVE_IMX_SRC
select IMX_HAVE_PLATFORM_IMX2_WDT
select PINCTRL_IMX53
select SOC_IMX5
help
This enables support for Freescale i.MX53 processor.
config SOC_IMX6Q
bool "i.MX6 Quad/DualLite support"
select ARCH_HAS_CPUFREQ
select ARCH_HAS_OPP
config SOC_IMX6
bool
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420
select ARM_GIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_IMX_ANATOP
select HAVE_IMX_GPC
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select MFD_SYSCON
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
select PINCTRL_IMX6Q
select PL310_ERRATA_588369 if CACHE_PL310
select PL310_ERRATA_727915 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310
select PM_OPP if PM
config SOC_IMX6Q
bool "i.MX6 Quad/DualLite support"
select ARM_ERRATA_764369 if SMP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
select PINCTRL_IMX6Q
select SOC_IMX6
help
This enables support for Freescale i.MX6 Quad processor.
config SOC_IMX6SL
bool "i.MX6 SoloLite support"
select ARM_ERRATA_754322
select ARM_ERRATA_775420
select ARM_GIC
select HAVE_IMX_ANATOP
select HAVE_IMX_GPC
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select MFD_SYSCON
select PINCTRL_IMX6SL
select PL310_ERRATA_588369 if CACHE_PL310
select PL310_ERRATA_727915 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310
select SOC_IMX6
help
This enables support for Freescale i.MX6 SoloLite processor.
......
arch/arm/mach-imx/Makefile
View file @ ff050ad1
......@@ -30,6 +30,7 @@ obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
endif
ifdef CONFIG_SND_IMX_SOC
......@@ -101,9 +102,11 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
# i.MX6SL reuses i.MX6Q code
obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
endif
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
# i.MX5 based machines
obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
......
arch/arm/mach-imx/clk-imx21.c
View file @ ff050ad1
......@@ -149,7 +149,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
......
arch/arm/mach-imx/clk-imx25.c
View file @ ff050ad1
......@@ -265,14 +265,6 @@ int __init mx25_clocks_init(void)
clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
......
arch/arm/mach-imx/clk-imx27.c
View file @ ff050ad1
......@@ -231,7 +231,6 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
......
arch/arm/mach-imx/clk-imx51-imx53.c
View file @ ff050ad1
......@@ -266,8 +266,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0");
clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1");
clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
......
arch/arm/mach-imx/clk-imx6q.c
View file @ ff050ad1
......@@ -437,12 +437,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
clk_register_clkdev(clk[ahb], "ahb", NULL);
clk_register_clkdev(clk[cko1], "cko1", NULL);
clk_register_clkdev(clk[arm], NULL, "cpu0");
clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
cpu_is_imx6dl()) {
......
arch/arm/mach-imx/clk-imx6sl.c
View file @ ff050ad1
/*
* Copyright 2013 Freescale Semiconductor, Inc.
* Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -18,27 +18,43 @@
#include "clk.h"
#include "common.h"
static const char const *step_sels[] = { "osc", "pll2_pfd2", };
static const char const *pll1_sw_sels[] = { "pll1_sys", "step", };
static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", };
static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
static const char const *perclk_sels[] = { "ipg", "osc", };
static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
static const char const *uart_sels[] = { "pll3_80m", "osc", };
#define CCSR 0xc
#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
#define CACRR 0x10
#define CDHIPR 0x48
#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16)
#define ARM_WAIT_DIV_396M 2
#define ARM_WAIT_DIV_792M 4
#define ARM_WAIT_DIV_996M 6
#define PLL_ARM 0x0
#define BM_PLL_ARM_DIV_SELECT (0x7f << 0)
#define BM_PLL_ARM_POWERDOWN (1 << 12)
#define BM_PLL_ARM_ENABLE (1 << 13)
#define BM_PLL_ARM_LOCK (1 << 31)
#define PLL_ARM_DIV_792M 66
static const char *step_sels[] = { "osc", "pll2_pfd2", };
static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
static const char *ocram_sels[] = { "periph", "ocram_alt_sels", };
static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
static const char *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
static const char *perclk_sels[] = { "ipg", "osc", };
static const char *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
static const char *ecspi_sels[] = { "pll3_60m", "osc", };
static const char *uart_sels[] = { "pll3_80m", "osc", };
static struct clk_div_table clk_enet_ref_table[] = {
{ .val = 0, .div = 20, },
......@@ -65,6 +81,89 @@ static struct clk_div_table video_div_table[] = {
static struct clk *clks[IMX6SL_CLK_END];
static struct clk_onecell_data clk_data;
static void __iomem *ccm_base;
static void __iomem *anatop_base;
static const u32 clks_init_on[] __initconst = {
IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
};
/*
* ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
* during WAIT mode entry process could cause cache memory
* corruption.
*
* Software workaround:
* To prevent this issue from occurring, software should ensure that the
* ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
* entering WAIT mode.
*
* This function will set the ARM clk to max value within the 12:5 limit.
* As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
* ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
* the clk APIs can NOT be called in idle thread(may cause kernel schedule
* as there is sleep function in PLL wait function), so here we just slow
* down ARM to below freq according to previous freq:
*
* run mode wait mode
* 396MHz -> 132MHz;
* 792MHz -> 158.4MHz;
* 996MHz -> 142.3MHz;
*/
static int imx6sl_get_arm_divider_for_wait(void)
{
if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
return ARM_WAIT_DIV_396M;
} else {
if ((readl_relaxed(anatop_base + PLL_ARM) &
BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
return ARM_WAIT_DIV_792M;
else
return ARM_WAIT_DIV_996M;
}
}
static void imx6sl_enable_pll_arm(bool enable)
{
static u32 saved_pll_arm;
u32 val;
if (enable) {
saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
val |= BM_PLL_ARM_ENABLE;
val &= ~BM_PLL_ARM_POWERDOWN;
writel_relaxed(val, anatop_base + PLL_ARM);
while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
;
} else {
writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
}
}
void imx6sl_set_wait_clk(bool enter)
{
static unsigned long saved_arm_div;
int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
/*
* According to hardware design, arm podf change need
* PLL1 clock enabled.
*/
if (arm_div_for_wait == ARM_WAIT_DIV_396M)
imx6sl_enable_pll_arm(true);
if (enter) {
saved_arm_div = readl_relaxed(ccm_base + CACRR);
writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
} else {
writel_relaxed(saved_arm_div, ccm_base + CACRR);
}
while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
;
if (arm_div_for_wait == ARM_WAIT_DIV_396M)
imx6sl_enable_pll_arm(false);
}
static void __init imx6sl_clocks_init(struct device_node *ccm_node)
{
......@@ -72,6 +171,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
void __iomem *base;
int irq;
int i;
int ret;
clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
......@@ -80,6 +180,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
base = of_iomap(np, 0);
WARN_ON(!base);
anatop_base = base;
/* type name parent base div_mask */
clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
......@@ -127,6 +228,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
np = ccm_node;
base = of_iomap(np, 0);
WARN_ON(!base);
ccm_base = base;
/* Reuse imx6q pm code */
imx6q_pm_set_ccm_base(base);
......@@ -258,6 +360,19 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
/* Ensure the AHB clk is at 132MHz. */
ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
if (ret)
pr_warn("%s: failed to set AHB clock rate %d!\n",
__func__, ret);
/*
* Make sure those always on clocks are enabled to maintain the correct
* usecount and enabling/disabling of parent PLLs.
*/
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
......
arch/arm/mach-imx/clk-vf610.c
View file @ ff050ad1
......@@ -63,25 +63,25 @@ static void __iomem *anatop_base;
static void __iomem *ccm_base;
/* sources for multiplexer clocks, this is used multiple times */
static const char const *fast_sels[] = { "firc", "fxosc", };
static const char const *slow_sels[] = { "sirc_32k", "sxosc", };
static const char const *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
static const char const *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
static const char const *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
static const char const *ddr_sels[] = { "pll2_pfd2", "sys_sel", };
static const char const *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
static const char const *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
static const char const *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
static const char const *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
static const char const *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
static const char const *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
static const char const *dcu_sels[] = { "pll1_pfd2", "pll3_main", };
static const char const *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", };
static const char const *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", };
static const char *fast_sels[] = { "firc", "fxosc", };
static const char *slow_sels[] = { "sirc_32k", "sxosc", };
static const char *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
static const char *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", };
static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
static const char *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
static const char *dcu_sels[] = { "pll1_pfd2", "pll3_main", };
static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", };
static const char *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", };
/* FTM counter clock source, not module clock */
static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
static struct clk_div_table pll4_main_div_table[] = {
{ .val = 0, .div = 1 },
......
arch/arm/mach-imx/common.h
View file @ ff050ad1
/*
* Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
......@@ -116,7 +116,6 @@ void imx_enable_cpu(int cpu, bool enable);
void imx_set_cpu_jump(int cpu, void *jump_addr);
u32 imx_get_cpu_arg(int cpu);
void imx_set_cpu_arg(int cpu, u32 arg);
void v7_cpu_resume(void);
#ifdef CONFIG_SMP
void v7_secondary_startup(void);
void imx_scu_map_io(void);
......@@ -139,13 +138,25 @@ void imx_anatop_init(void);
void imx_anatop_pre_suspend(void);
void imx_anatop_post_resume(void);
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
void imx6q_set_chicken_bit(void);
void imx6q_set_int_mem_clk_lpm(void);
void imx6sl_set_wait_clk(bool enter);
void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);
#ifdef CONFIG_SUSPEND
void v7_cpu_resume(void);
void imx6_suspend(void __iomem *ocram_vbase);
#else
static inline void v7_cpu_resume(void) {}
static inline void imx6_suspend(void __iomem *ocram_vbase) {}
#endif
void imx6q_pm_init(void);
void imx6dl_pm_init(void);
void imx6sl_pm_init(void);
void imx6q_pm_set_ccm_base(void __iomem *base);
#ifdef CONFIG_PM
void imx5_pm_init(void);
#else
......
arch/arm/mach-imx/cpuidle-imx6q.c
View file @ ff050ad1
......@@ -68,8 +68,8 @@ int __init imx6q_cpuidle_init(void)
/* Need to enable SCU standby for entering WAIT modes */
imx_scu_standby_enable();
/* Set chicken bit to get a reliable WAIT mode support */
imx6q_set_chicken_bit();
/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
imx6q_set_int_mem_clk_lpm();
return cpuidle_register(&imx6q_cpuidle_driver, NULL);
}
arch/arm/mach-imx/cpuidle-imx6sl.c 0 → 100644
View file @ ff050ad1
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/cpuidle.h>
#include <linux/module.h>
#include <asm/cpuidle.h>
#include <asm/proc-fns.h>
#include "common.h"
#include "cpuidle.h"
static int imx6sl_enter_wait(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
imx6q_set_lpm(WAIT_UNCLOCKED);
/*
* Software workaround for ERR005311, see function
* description for details.
*/
imx6sl_set_wait_clk(true);
cpu_do_idle();
imx6sl_set_wait_clk(false);
imx6q_set_lpm(WAIT_CLOCKED);
return index;
}
static struct cpuidle_driver imx6sl_cpuidle_driver = {
.name = "imx6sl_cpuidle",
.owner = THIS_MODULE,
.states = {
/* WFI */
ARM_CPUIDLE_WFI_STATE,
/* WAIT */
{
.exit_latency = 50,
.target_residency = 75,
.flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_TIMER_STOP,
.enter = imx6sl_enter_wait,
.name = "WAIT",
.desc = "Clock off",
},
},
.state_count = 2,
.safe_state_index = 0,
};
int __init imx6sl_cpuidle_init(void)
{
return cpuidle_register(&imx6sl_cpuidle_driver, NULL);
}
arch/arm/mach-imx/cpuidle.h
View file @ ff050ad1
......@@ -13,6 +13,7 @@
#ifdef CONFIG_CPU_IDLE
extern int imx5_cpuidle_init(void);
extern int imx6q_cpuidle_init(void);
extern int imx6sl_cpuidle_init(void);
#else
static inline int imx5_cpuidle_init(void)
{
......@@ -22,4 +23,8 @@ static inline int imx6q_cpuidle_init(void)
{
return 0;
}
static inline int imx6sl_cpuidle_init(void)
{
return 0;
}
#endif
arch/arm/mach-imx/devices-imx25.h
View file @ ff050ad1
......@@ -83,7 +83,3 @@ extern const struct imx_spi_imx_data imx25_cspi_data[];
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
#define imx25_add_mxc_pwm(id) \
imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
arch/arm/mach-imx/devices-imx51.h
View file @ ff050ad1
......@@ -57,10 +57,6 @@ extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
#define imx51_add_imx2_wdt(id) \
imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
#define imx51_add_mxc_pwm(id) \
imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
#define imx51_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
......
arch/arm/mach-imx/devices/Kconfig
View file @ ff050ad1
......@@ -67,9 +67,6 @@ config IMX_HAVE_PLATFORM_MXC_MMC
config IMX_HAVE_PLATFORM_MXC_NAND
bool
config IMX_HAVE_PLATFORM_MXC_PWM
bool
config IMX_HAVE_PLATFORM_MXC_RNGA
bool
select ARCH_HAS_RNGA
......
arch/arm/mach-imx/devices/Makefile
View file @ ff050ad1
......@@ -23,7 +23,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
......
arch/arm/mach-imx/devices/devices-common.h
View file @ ff050ad1
......@@ -290,15 +290,6 @@ struct imx_pata_imx_data {
struct platform_device *__init imx_add_pata_imx(
const struct imx_pata_imx_data *data);
struct imx_mxc_pwm_data {
int id;
resource_size_t iobase;
resource_size_t iosize;
resource_size_t irq;
};
struct platform_device *__init imx_add_mxc_pwm(
const struct imx_mxc_pwm_data *data);
/* mxc_rtc */
struct imx_mxc_rtc_data {
const char *devid;
......
arch/arm/mach-imx/devices/platform-mxc_pwm.c deleted 100644 → 0
View file @ dfc25e45
/*
* Copyright (C) 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include "../hardware.h"
#include "devices-common.h"
#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \
{ \
.id = _id, \
.iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_PWM ## _hwid, \
}
#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \
[_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
#ifdef CONFIG_SOC_IMX21
const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
#define imx25_mxc_pwm_data_entry(_id, _hwid) \
imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
imx25_mxc_pwm_data_entry(0, 1),
imx25_mxc_pwm_data_entry(1, 2),
imx25_mxc_pwm_data_entry(2, 3),
imx25_mxc_pwm_data_entry(3, 4),
};
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX51
const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = {
#define imx51_mxc_pwm_data_entry(_id, _hwid) \
imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K)
imx51_mxc_pwm_data_entry(0, 1),
imx51_mxc_pwm_data_entry(1, 2),
};
#endif /* ifdef CONFIG_SOC_IMX51 */
struct platform_device *__init imx_add_mxc_pwm(
const struct imx_mxc_pwm_data *data)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + data->iosize - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device("mxc_pwm", data->id,
res, ARRAY_SIZE(res), NULL, 0);
}
arch/arm/mach-imx/hardware.h
View file @ ff050ad1
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
......@@ -20,7 +20,9 @@
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#define __ASM_ARCH_MXC_HARDWARE_H__
#ifndef __ASSEMBLY__
#include <asm/io.h>
#endif
#include <asm/sizes.h>
#define addr_in_module(addr, mod) \
......
arch/arm/mach-imx/headsmp.S
View file @ ff050ad1
......@@ -12,12 +12,7 @@
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/asm-offsets.h>
#include <asm/hardware/cache-l2x0.h>
.section ".text.head", "ax"
#ifdef CONFIG_SMP
diag_reg_offset:
.word g_diag_reg - .
......@@ -34,38 +29,3 @@ ENTRY(v7_secondary_startup)
set_diag_reg
b secondary_startup
ENDPROC(v7_secondary_startup)
#endif
#ifdef CONFIG_ARM_CPU_SUSPEND
/*
* The following code must assume it is running from physical address
* where absolute virtual addresses to the data section have to be
* turned into relative ones.
*/
#ifdef CONFIG_CACHE_L2X0
.macro pl310_resume
adr r0, l2x0_saved_regs_offset
ldr r2, [r0]
add r2, r2, r0
ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value
str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl
mov r1, #0x1
str r1, [r0, #L2X0_CTRL] @ re-enable L2
.endm
l2x0_saved_regs_offset:
.word l2x0_saved_regs - .
#else
.macro pl310_resume
.endm
#endif
ENTRY(v7_cpu_resume)
bl v7_invalidate_l1
pl310_resume
b cpu_resume
ENDPROC(v7_cpu_resume)
#endif
arch/arm/mach-imx/mach-imx6q.c
View file @ ff050ad1
......@@ -182,16 +182,83 @@ static void __init imx6q_enet_phy_init(void)
static void __init imx6q_1588_init(void)
{
struct device_node *np;
struct clk *ptp_clk;
struct clk *enet_ref;
struct regmap *gpr;
u32 clksel;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
if (!np) {
pr_warn("%s: failed to find fec node\n", __func__);
return;
}
ptp_clk = of_clk_get(np, 2);
if (IS_ERR(ptp_clk)) {
pr_warn("%s: failed to get ptp clock\n", __func__);
goto put_node;
}
enet_ref = clk_get_sys(NULL, "enet_ref");
if (IS_ERR(enet_ref)) {
pr_warn("%s: failed to get enet clock\n", __func__);
goto put_ptp_clk;
}
/*
* If enet_ref from ANATOP/CCM is the PTP clock source, we need to
* set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
* (external OSC), and we need to clear the bit.
*/
clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
IMX6Q_GPR1_ENET_CLK_SEL_PAD;
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
if (!IS_ERR(gpr))
regmap_update_bits(gpr, IOMUXC_GPR1,
IMX6Q_GPR1_ENET_CLK_SEL_MASK,
IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
clksel);
else
pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
clk_put(enet_ref);
put_ptp_clk:
clk_put(ptp_clk);
put_node:
of_node_put(np);
}
static void __init imx6q_axi_init(void)
{
struct regmap *gpr;
unsigned int mask;
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
if (!IS_ERR(gpr)) {
/*
* Enable the cacheable attribute of VPU and IPU
* AXI transactions.
*/
mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL |
IMX6Q_GPR4_VPU_RD_CACHE_SEL |
IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
IMX6Q_GPR4_IPU_WR_CACHE_CTL |
IMX6Q_GPR4_IPU_RD_CACHE_CTL;
regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);
/* Increase IPU read QoS priority */
regmap_update_bits(gpr, IOMUXC_GPR6,
IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
(0xf << 16) | (0x7 << 20));
regmap_update_bits(gpr, IOMUXC_GPR7,
IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
(0xf << 16) | (0x7 << 20));
} else {
pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
}
}
static void __init imx6q_init_machine(void)
......@@ -212,15 +279,18 @@ static void __init imx6q_init_machine(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
imx_anatop_init();
imx6q_pm_init();
cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
imx6q_1588_init();
imx6q_axi_init();
}
#define OCOTP_CFG3 0x440
#define OCOTP_CFG3_SPEED_SHIFT 16
#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
#define OCOTP_CFG3_SPEED_996MHZ 0x2
#define OCOTP_CFG3_SPEED_852MHZ 0x1
static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
{
struct device_node *np;
void __iomem *base;
......@@ -238,11 +308,29 @@ static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
goto put_node;
}
/*
* SPEED_GRADING[1:0] defines the max speed of ARM:
* 2b'11: 1200000000Hz;
* 2b'10: 996000000Hz;
* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
* 2b'00: 792000000Hz;
* We need to set the max speed of ARM according to fuse map.
*/
val = readl_relaxed(base + OCOTP_CFG3);
val >>= OCOTP_CFG3_SPEED_SHIFT;
if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
val &= 0x3;
if (val != OCOTP_CFG3_SPEED_1P2GHZ)
if (dev_pm_opp_disable(cpu_dev, 1200000000))
pr_warn("failed to disable 1.2 GHz OPP\n");
if (val < OCOTP_CFG3_SPEED_996MHZ)
if (dev_pm_opp_disable(cpu_dev, 996000000))
pr_warn("failed to disable 996 MHz OPP\n");
if (cpu_is_imx6q()) {
if (val != OCOTP_CFG3_SPEED_852MHZ)
if (dev_pm_opp_disable(cpu_dev, 852000000))
pr_warn("failed to disable 852 MHz OPP\n");
}
put_node:
of_node_put(np);
......@@ -268,7 +356,7 @@ static void __init imx6q_opp_init(void)
goto put_node;
}
imx6q_opp_check_1p2ghz(cpu_dev);
imx6q_opp_check_speed_grading(cpu_dev);
put_node:
of_node_put(np);
......
arch/arm/mach-imx/mach-imx6sl.c
View file @ ff050ad1
......@@ -17,6 +17,7 @@
#include <asm/mach/map.h>
#include "common.h"
#include "cpuidle.h"
static void __init imx6sl_fec_init(void)
{
......@@ -39,6 +40,8 @@ static void __init imx6sl_init_late(void)
/* imx6sl reuses imx6q cpufreq driver */
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
imx6sl_cpuidle_init();
}
static void __init imx6sl_init_machine(void)
......@@ -55,8 +58,7 @@ static void __init imx6sl_init_machine(void)
imx6sl_fec_init();
imx_anatop_init();
/* Reuse imx6q pm code */
imx6q_pm_init();
imx6sl_pm_init();
}
static void __init imx6sl_init_irq(void)
......
arch/arm/mach-imx/suspend-imx6.S 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-imx/time.c
View file @ ff050ad1
......@@ -25,6 +25,7 @@
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
......@@ -116,11 +117,22 @@ static u64 notrace mxc_read_sched_clock(void)
return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
}
static struct delay_timer imx_delay_timer;
static unsigned long imx_read_current_timer(void)
{
return __raw_readl(sched_clock_reg);
}
static int __init mxc_clocksource_init(struct clk *timer_clk)
{
unsigned int c = clk_get_rate(timer_clk);
void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
imx_delay_timer.read_current_timer = &imx_read_current_timer;
imx_delay_timer.freq = c;
register_current_timer_delay(&imx_delay_timer);
sched_clock_reg = reg;
sched_clock_register(mxc_read_sched_clock, 32, c);
......
arch/arm/mach-kirkwood/Kconfig
View file @ ff050ad1
......@@ -106,13 +106,6 @@ config ARCH_KIRKWOOD_DT
Say 'Y' here if you want your kernel to support the
Marvell Kirkwood using flattened device tree.
config MACH_MV88F6281GTW_GE_DT
bool "Marvell 88F6281 GTW GE Board (Flattened Device Tree)"
depends on ARCH_KIRKWOOD_DT
help
Say 'Y' here if you want your kernel to support the
Marvell 88F6281 GTW GE Board (Flattened Device Tree).
endmenu
endif
arch/arm/mach-kirkwood/Makefile
View file @ ff050ad1
obj-y += common.o pcie.o
obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o
obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o common.o pcie.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o
......@@ -13,4 +12,3 @@ obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o
obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o
obj-$(CONFIG_MACH_MV88F6281GTW_GE_DT) += board-mv88f6281gtw_ge.o
arch/arm/mach-kirkwood/board-dt.c
View file @ ff050ad1
......@@ -19,11 +19,84 @@
#include <linux/of_platform.h>
#include <linux/dma-mapping.h>
#include <linux/irqchip.h>
#include <linux/kexec.h>
#include <asm/hardware/cache-feroceon-l2.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/bridge-regs.h>
#include <plat/common.h>
#include "common.h"
#include <plat/pcie.h>
#include "pm.h"
static struct map_desc kirkwood_io_desc[] __initdata = {
{
.virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
.length = KIRKWOOD_REGS_SIZE,
.type = MT_DEVICE,
},
};
static void __init kirkwood_map_io(void)
{
iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
}
static struct resource kirkwood_cpufreq_resources[] = {
[0] = {
.start = CPU_CONTROL_PHYS,
.end = CPU_CONTROL_PHYS + 3,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device kirkwood_cpufreq_device = {
.name = "kirkwood-cpufreq",
.id = -1,
.num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources),
.resource = kirkwood_cpufreq_resources,
};
static void __init kirkwood_cpufreq_init(void)
{
platform_device_register(&kirkwood_cpufreq_device);
}
static struct resource kirkwood_cpuidle_resource[] = {
{
.flags = IORESOURCE_MEM,
.start = DDR_OPERATION_BASE,
.end = DDR_OPERATION_BASE + 3,
},
};
static struct platform_device kirkwood_cpuidle = {
.name = "kirkwood_cpuidle",
.id = -1,
.resource = kirkwood_cpuidle_resource,
.num_resources = 1,
};
static void __init kirkwood_cpuidle_init(void)
{
platform_device_register(&kirkwood_cpuidle);
}
/* Temporary here since mach-mvebu has a function we can use */
static void kirkwood_restart(enum reboot_mode mode, const char *cmd)
{
/*
* Enable soft reset to assert RSTOUTn.
*/
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
/*
* Assert soft reset.
*/
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
while (1)
;
}
#define MV643XX_ETH_MAC_ADDR_LOW 0x0414
#define MV643XX_ETH_MAC_ADDR_HIGH 0x0418
......@@ -104,35 +177,35 @@ static void __init kirkwood_dt_eth_fixup(void)
}
}
static void __init kirkwood_dt_init(void)
/*
* Disable propagation of mbus errors to the CPU local bus, as this
* causes mbus errors (which can occur for example for PCI aborts) to
* throw CPU aborts, which we're not set up to deal with.
*/
static void __init kirkwood_disable_mbus_error_propagation(void)
{
pr_info("Kirkwood: %s.\n", kirkwood_id());
void __iomem *cpu_config;
/*
* Disable propagation of mbus errors to the CPU local bus,
* as this causes mbus errors (which can occur for example
* for PCI aborts) to throw CPU aborts, which we're not set
* up to deal with.
*/
writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
cpu_config = ioremap(CPU_CONFIG_PHYS, 4);
writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config);
iounmap(cpu_config);
}
BUG_ON(mvebu_mbus_dt_init());
static void __init kirkwood_dt_init(void)
{
kirkwood_disable_mbus_error_propagation();
kirkwood_l2_init();
BUG_ON(mvebu_mbus_dt_init());
#ifdef CONFIG_CACHE_FEROCEON_L2
feroceon_of_init();
#endif
kirkwood_cpufreq_init();
kirkwood_cpuidle_init();
kirkwood_pm_init();
kirkwood_dt_eth_fixup();
#ifdef CONFIG_KEXEC
kexec_reinit = kirkwood_enable_pcie;
#endif
if (of_machine_is_compatible("marvell,mv88f6281gtw-ge"))
mv88f6281gtw_ge_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
......
arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c deleted 100644 → 0
View file @ dfc25e45
This diff is collapsed.
arch/arm/mach-kirkwood/common.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-kirkwood/common.h
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-kirkwood/pm.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-msm/common.h
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mv78xx0/common.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/Kconfig
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/Makefile
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/board-t5325.c 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/board.h 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/kirkwood-pm.c 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/kirkwood-pm.h 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/kirkwood.c 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/kirkwood.h 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/mvebu-soc-id.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-mvebu/system-controller.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/Kconfig
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/Makefile
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/board-generic.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/clkt_dpll.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/cminst44xx.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/dpll3xxx.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/id.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/io.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/mux.h
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/prminst44xx.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/soc.h
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-omap2/timer.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-qcom/board.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-qcom/platsmp.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-qcom/scm-boot.h
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-rockchip/Kconfig
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-rockchip/Makefile
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-rockchip/core.h 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-rockchip/headsmp.S 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-rockchip/platsmp.c 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-rockchip/rockchip.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/Kconfig
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/Makefile
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/include/mach/pm-rcar.h 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/platsmp-apmu.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/pm-r8a7779.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/pm-r8a7790.c 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/pm-rcar.c 0 → 100644
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/setup-rcar-gen2.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/smp-r8a7779.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-shmobile/smp-r8a7790.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-sunxi/Kconfig
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-sunxi/sunxi.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-tegra/Makefile
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-tegra/cpuidle-tegra114.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-tegra/platsmp.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-tegra/powergate.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mach-tegra/tegra2_emc.c deleted 100644 → 0
View file @ dfc25e45
This diff is collapsed.
arch/arm/mm/Kconfig
View file @ ff050ad1
This diff is collapsed.
arch/arm/mm/cache-feroceon-l2.c
View file @ ff050ad1
This diff is collapsed.
arch/arm/mm/cache-tauros2.c
View file @ ff050ad1
This diff is collapsed.
drivers/bus/imx-weim.c
View file @ ff050ad1
This diff is collapsed.
drivers/irqchip/Kconfig
View file @ ff050ad1
This diff is collapsed.
drivers/irqchip/Makefile
View file @ ff050ad1
This diff is collapsed.
drivers/irqchip/irq-clps711x.c 0 → 100644
View file @ ff050ad1
This diff is collapsed.
include/asm-generic/vmlinux.lds.h
View file @ ff050ad1
This diff is collapsed.
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
View file @ ff050ad1
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7