- 09 Sep, 2014 40 commits
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Doug Anderson authored
For UHS cards we need the ability to switch voltages from 3.3V to 1.8V. Add support to the dw_mmc driver to handle this. Note that dw_mmc needs a little bit of extra code since the interface needs a special bit programmed to the CMD register while CMD11 is progressing. This means adding a few extra states to the state machine to track. Signed-off-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Yuvaraj CD authored
This patch makes use of mmc_regulator_get_supply() to handle the vmmc and vqmmc regulators.Also it moves the code handling the these regulators to dw_mci_set_ios().It turned on the vmmc and vqmmc during MMC_POWER_UP and MMC_POWER_ON,and turned off during MMC_POWER_OFF. Signed-off-by:
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Chuanxiao Dong authored
With one special SD card, below divide by zero error observed: ... [ 2.144300] divide error: 0000 [#1] PREEMPT SMP [ 2.148860] Modules linked in: [ 2.151898] [ 2.152685] Set up 4031 stolen pages starting at 0x0001f000, GTT offset 0K [ 2.157330] Set up 0 CI stolen pages starting at 0x00000000, GTT offset 131072K [ 2.167581] Pid: 5, comm: kworker/u:0 Not tainted 3.0.8-138216-g974a2aba #1 [ 2.169506] [drm] PSB GTT mem manager ready, tt_start 4031, tt_size 28737 pages [ 2.169906] [drm] SGX core id = 0x00000000 [ 2.169920] [drm] SGX core rev major = 0x00, minor = 0x00 [ 2.169934] [drm] SGX core rev maintenance = 0x00, designer = 0x00 [ 2.197370] Intel Corporation Medfield/iCDKB [ 2.201716] EIP: 0060:[<c1697ca6>] EFLAGS: 00010246 CPU: 1 [ 2.207198] EIP is at mmc_init_erase+0x76/0x150 [ 2.211704] EAX: 00002000 EBX: dcd1b400 ECX: 00002000 EDX: 00000000 [ 2.217957] ESI: 00000000 EDI: dcd5c800 EBP: dd867e84 ESP: dd867e7c [ 2.224214] DS: 007b ES: 007b FS: 00d8 GS: 0000 SS: 0068 [ 2.229605] Process kworker/u:0 (pid: 5, ti=dd866000 task=dd868000 task.ti=dd866000) [ 2.237325] Stack: [ 2.239322] dcd1b400 00000000 dd867eb0 c16a06da c1ab7c44 dd995aa8 00000003 00000000 [ 2.247054] 00000000 00000000 dcd5c800 00000000 dcd1b400 dd867ef8 c16a1012 c1698b00 [ 2.254785] 00000029 00000001 c194eb80 dcd5c9ec dd867e00 c1239b00 00000000 00000000 [ 2.262519] Call Trace: [ 2.264975] [<c16a06da>] mmc_sd_setup_card+0x1da/0x4f0 [ 2.270183] [<c16a1012>] mmc_sd_init_card+0x192/0xc40 [ 2.275304] [<c1698b00>] ? __mmc_claim_host+0x160/0x160 [ 2.280610] [<c1239b00>] ? __schedule_bug+0x50/0x80 [ 2.285556] [<c16a1b89>] mmc_attach_sd+0xc9/0x230 [ 2.290333] [<c169b6ef>] mmc_rescan+0x25f/0x2c0 [ 2.294943] [<c1274223>] process_one_work+0x103/0x400 [ 2.300065] [<c12670fd>] ? mod_timer+0x1ad/0x3c0 [ 2.304756] [<c169b490>] ? mmc_suspend_host+0x1a0/0x1a0 [ 2.310056] [<c127502d>] worker_thread+0x12d/0x4a0 [ 2.314921] [<c18fcfbd>] ? preempt_schedule+0x2d/0x50 [ 2.320047] [<c1274f00[ 2.323976] ---[ end trace 5398ec2720494438 ]--- ... So, seems this bad SD card does not set valid value in related SSR / CSD register fields. And then the driver will set card->erase_size to 0. Then it triggered this divided by zero error when calculate card->pref_erase. Submit this patch to fix the issue. Signed-off-by:
Yunpeng Gao <yunpeng.gao@intel.com> Signed-off-by:
Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by:
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Chen-Yu Tsai authored
Declare ERASE capability so we can use filesystems with the discard option and the fstrim tool. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Alan Cox authored
The hardware is the same as used in Baytrail. Add these new PCI IDs to the driver's list of supported IDs. Signed-off-by:
Alan Cox <alan@linux.intel.com> Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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addy ke authored
To support HS200 and UHS-1, we need add a big hunk of code, as shown in the following patches. So a separate file for rockchip SOCs is suitable. Signed-off-by:
Addy Ke <addy.ke@rock-chips.com> Acked-by:
Jaehoon Chung <jh80.chung@samsung.com> Tested-by:
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Shinobu Uehara authored
Some controller is supporting actual clock on SD_CLK_CTRL :: DIV[7:0]. Renesas SH-Mobile SDHI doesn't support, but, Renesas R-Car SDHI supports it. This patch adds new TMIO_MMC_CLK_ACTUAL flag for it. [Kuninori Morimoto: tidyuped for upstreaming] Tested-by:
Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by:
Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by:
Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
TMIO clock is set via tmio_mmc_set_clock() -> tmio_mmc_clk_start(), and SCLKEN bit will be set on tmio_mmc_clk_start(). It is not needed on tmio_mmc_set_clock() function. The required clock setting will not be able to set in some clocks without this patch. Tested-by:
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Kuninori Morimoto authored
This patch adds new TMIO_MMC_HAVE_CTL_DMA_REG flag, and remove Renesas specific #ifdef from tmio driver Tested-by:
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Shinobu Uehara authored
Some controllers need to check SD bus status when writing data. Then, it checks ILL_FUNC bit on SD_INFO2 register, and this method is controlled via TMIO_MMC_HAS_IDLE_WAIT flags. Same method is required on tmio_mmc_data_irq() which will be called after writing data. Current driver is checking CBSY bit for this purpose, but, some controllers doesn't have CBSY bit. This patch checks ILL_FUNC bit instead of CBSY bit if it has TMIO_MMC_HAS_IDLE_WAIT flags [Kuninori Morimoto: tidyuped for upstreaming] Tested-by:
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Shinobu Uehara authored
Renesas R-Car SDHI should set reserved bits on CTL_SDIO_STATUS register when writing. This patch adds new TMIO_MMC_SDIO_STATUS_QUIRK flags for this purpose [Kuninori Morimoto: tidyuped for upstreaming enabled this flags for all SH-Mobile/R-Car] Tested-by: -
Shinobu Uehara authored
Renesas SDHI has "Multiple Block Transfer Mode" settings on SD_CMD register which controls CMD12 automatically. This patch cares it, because CMD12 is not needed when CMD53 (= SD_IO_RW_EXTENDED) [Kuninori Morimoto: tidyuped for upstreaming enabled this flags for all SH-Mobile/R-Car] Tested-by: -
Shinobu Uehara authored
Next card access will be always error if it didn't clear error status Tested-by:
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Kuninori Morimoto authored
Basically, SD_BUF0 Tx/Rx addresses are same in normal TMIO controller, but, it is different on Renesas R-Car SDHI controller if it uses DMAC (Rx address needs to add 0x2000 to Tx address) This patch adds new .dma_rx_offset and cares it Tested-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by:
Ben Dooks <ben-linux@fluff.org> Signed-off-by:
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Ulf Hansson authored
These library functions aren't used and nor needed, let's remove them. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Ulf Hansson authored
At system PM suspend, the tmio core accessed the internal registers of the controller without first moving the device into active state. This caused a lock-up in system PM suspend phase. The reason for the register access were masking of IRQs. Since that is managed via the runtime PM suspend path, let's just re-use that path for system PM suspend. In other words force the device into runtime PM suspend state at system PM suspend and restore it to active state at system PM resume. Reported-by:
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Ulf Hansson authored
At system PM suspend, the tmio core accessed the internal registers of the controller without first moving the device into active state. This caused a lock-up in system PM suspend phase. The reason for the register access were masking of IRQs. Since that is managed via the runtime PM suspend path, let's just re-use that path for system PM suspend. In other words force the device into runtime PM suspend state at system PM suspend and restore it to active state at system PM resume. Reported-by:
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Ulf Hansson authored
To take advantage of the clock gating support, use the runtime PM callbacks provided by the tmio core. Additionally, we make use of the SET_PM_RUNTIME_PM_OPS, which is a preparation needed to simplify system PM. Signed-off-by:
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Ulf Hansson authored
To be able to simplify system PM, let's re-use the runtime PM callbacks by converting to the SET_PM_RUNTIME_PM_OPS macro. Signed-off-by:
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Ulf Hansson authored
To give the option for tmio hosts to use the runtime PM callbacks for CONFIG_PM_SLEEP as well as CONFIG_PM_RUNTIME, move them to CONFIG_PM. Signed-off-by:
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Ulf Hansson authored
To make sure we don't receive any spurious IRQs while we are inactive, mask the IRQs from within the ->runtime_suspend() callback. Signed-off-by:
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Ulf Hansson authored
Add clock gating control as a part of the tmio library functions for runtime PM. Signed-off-by:
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Ulf Hansson authored
An internal power state machine were beeing used to keep ->probe() and ->set_ios() in sync. Especially for handling specific scenarios while using CONFIG_MMC_CLKGATE. Moreover dependency to CONFIG_MMC_CLKGATE existed to handle runtime PM properly, which we moves away from here. By removing the state machine and instead make ->set_ios() rely on the information provided through the function's in-parameters, the code becomes significantly simplier. Additonally as a part of this rework we prepares for making the runtime PM callbacks responsible of clock gating. Signed-off-by:
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Ulf Hansson authored
Move code for bus_width modification, out of the ->set_ios() callback and into a separate function, to simplify code. Signed-off-by:
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Ulf Hansson authored
Use runtime PM to keep the host active during I/O operations and other requests which requires the tmio hardware to be powered. Additionally make use of the runtime PM autosuspend feature with a default timeout of 50 ms. Signed-off-by:
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Ulf Hansson authored
The host must be kept active to be able to serve SDIO IRQs, thus let's prevent it from going inactive while SDIO IRQ is enabled. Signed-off-by:
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Nicolas Ferre authored
Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
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Javier Martinez Canillas authored
The operation conditions register (OCR) stores the voltage profile of the card, however the list of possible voltages is restricted by the voltage range supported by the supply used as VCC/VDD. So in mmc_vddrange_to_ocrmask() a OCR mask is obtained to filter the not supported voltages, from the value read in the host controller OCR register. For fixed regulators, regulator_list_voltage() returns the fixed output for the first selector but this doesn't happen for switch (FET) regulators that obtain their voltage from their parent supply. A call to regulator_get_voltage() is needed in this case so the regulator core can return the FET's parent supply voltage output. This change is consistent with the fact that for other fixed regulators (that are not FETs) the OCR mask is returned even when mmc_regulator_set_ocr() checks if the regulator is fixed before calling regulator_set_voltage(). Without this patch, the following warning is reported when a FET is used as a vmmc-supply: dwmmc_exynos 12220000.mmc: Failed getting OCR mask: -22 Signed-off-by:
Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by:
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Sascha Hauer authored
Some eMMC and SD cards implement a DSR register that allows to tune raise/fall times and drive strength of the CMD and DATA outputs. The values to use depend on the card in use and the host. It might be needed to reduce the drive strength to prevent voltage peaks above the host's specification. Implement a 'dsr' devicetree property that allows to specify the value to set the DSR to. For non-dt setups the new members of mmc_host can be set by board code. This patch was initially authored by Sascha Hauer. It contains improvements authored by Markus Niebel and Uwe Kleine-König. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Markus Niebel <Markus.Niebel@tq-group.com> Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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Peter Griffin authored
.set_uhs_signaling field is currently initialised twice once to the arch specific callback pxav3_set_uhs_signaling, and also to the generic sdhci_set_uhs_signaling callback. This means that uhs is currently broken for this platform currently, as pxav3 has some special constriants which means it can't use the generic callback. This happened in commit 96d7b78c ("mmc: sdhci: convert sdhci_set_uhs_signaling() into a library function") commit a702c8ab ("mmc: host: split up sdhci-pxa, create sdhci-pxav3.c")' Fix this and hopefully prevent it happening in the future by ensuring named initialisers always follow the declaration order in the structure definition. Signed-off-by:
Peter Griffin <peter.griffin@linaro.org> Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by:
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Peter Griffin authored
This allows us to get rid of the #else condition, as the macro compiles away to nothing if not enabled. Signed-off-by:
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Peter Griffin authored
This allows us to get rid of the #else condition, as the macro compiles away to nothing if not enabled. Signed-off-by:
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Peter Griffin authored
As the code is using SIMPLE_DEV_PM_OPS helper, this compiles away to nothing if CONFIG_PM_SLEEP is disabled. Thus we don't need to #define the suspend/resume callbacks to NULL. Signed-off-by:
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Peter Griffin authored
As the code is using SIMPLE_DEV_PM_OPS helper, this compiles away to nothing if CONFIG_PM_SLEEP is disabled. Thus we don't need to #define the suspend/resume callbacks to NULL. Signed-off-by:
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Peter Griffin authored
This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway. Signed-off-by:
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Fu Zhonghui authored
781e989c ("mmc: sdhci: convert to new SDIO IRQ handling") and bf3b5ec6 ("mmc: sdio_irq: rework sdio irq handling") disabled the use of our own custom threaded IRQ handler, but left in an unconditional wake_up_process() on that handler at resume-time. Link: https://bugzilla.kernel.org/show_bug.cgi?id=80151 In addition, the check for MMC_CAP_SDIO_IRQ capability is added before enable sdio IRQ. Signed-off-by:
Chris Ball <chris@printf.net> Signed-off-by:
Fu Zhonghui <zhonghui.fu@linux.intel.com> Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by:
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Andrew Bresticker authored
There are upcoming MIPS SoCs with dw_mmc hosts. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Reviewed-by:
Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by:
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Andrew Bresticker authored
The dw_mmc drivers rely on the DMA API, so update the Kconfig entry to depend on HAS_DMA. Since the drivers should build on any platform with DMA, allow the driver to compile tested on non-ARC/ARM platforms. Signed-off-by:
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Matthieu CASTET authored
when SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set, timeout_clk is sdclk. We need to update it when we change sdclk in sdhci_set_clock. This allow to have a more precisse timeout and max_busy_timeout. This can help for command that need a big busy wait (erase, ...). Signed-off-by:
Matthieu CASTET <matthieu.castet@parrot.com> Signed-off-by:
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Matthieu CASTET authored
When we wait for busy after sending a command, if there is a timeout, we got SDHCI_INT_DATA_TIMEOUT flags. Before this commit we got the message : "Got data interrupt 0x00100000 even though no data operation was in progress." and we need to wait 10s that sdhci_timeout_timer expires. Signed-off-by:
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