- 12 Sep, 2018 4 commits
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David Francis authored
DMCU (Display Microcontroller Unit) is a GPU chip involved in eDP features like Adaptive Backlight Modulation and Panel Self Refresh. DMCU has two pieces of firmware: the ERAM and the interrupt vectors, which must be loaded seperately. To this end, the DMCU firmware has a custom header and parsing logic similar to MEC, to extract the two ucodes from a single struct firmware. Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Oak Zeng authored
In stead of share one fault hash table per device, make it per vm. This can avoid inter-process lock issue when fault hash table is full. Change-Id: I5d1281b7c41eddc8e26113e010516557588d3708 Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Suggested-by:
Christian Konig <Christian.Koenig@amd.com> Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Chunming Zhou authored
cs dependencies handling doesn't need in vm resv Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Christian König authored
Try to allocate VRAM in power of two sizes and only fallback to vram split sizes if that fails. Signed-off-by:
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- 11 Sep, 2018 36 commits
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Andrey Grodzovsky authored
After GPU reset amdgpu_vm_clear_bo triggers VM flush but job->vm_pd_addr is not set causing SDMA TO. v2: Per advise by Christian König avoid flushing VM for jobs where job->vm_pd_addr wasn't explicitly set. v3: Shortcut vm_flush_needed early. Fixes cbd52851 drm/amdgpu: move setting the GART addr into TTM. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Christian König authored
Add helper to call the update function for both BO and shadow. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Christian König authored
Add a function to get the parent of a PD/PT. Signed-off-by:
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Christian König authored
Slowly leaking memory one page at a time :) Signed-off-by:
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shaoyunl authored
v2: compile fix Signed-off-by:
shaoyunl <Shaoyun.Liu@amd.com> Reviewed-by:
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Shaoyun Liu authored
Generate xGMI iolink for upper level usage Signed-off-by:
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Shaoyun Liu authored
Update the iolink type defines according to the new thunk spec Signed-off-by:
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Shaoyun Liu authored
Thunk will generate the XGMI topology information when necessary with the hive_id for each specified device Signed-off-by:
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Shaoyun Liu authored
Retrieve hive_id from amdgpu device v2: compile fix Signed-off-by:
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Shaoyun Liu authored
KFD need to get hive id from amdgpu to build up the XGMI topology Signed-off-by:
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Shaoyun Liu authored
Driver will save an array of XGMI hive info, each hive will have a list of devices that have the same hive ID. Signed-off-by:
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Shaoyun Liu authored
Add dummy function for xgmi function interface with psp Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Shaoyun Liu authored
Place holder for XGMI support Signed-off-by:
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Alex Deucher authored
On hives with xgmi enabled, the fb_location aperture is a size which defines the total framebuffer size of all nodes in the hive. Each GPU in the hive has the same view via the fb_location aperture. GPU0 starts at offset (0 * segment size), GPU1 starts at offset (1 * segment size), etc. For access to local vram on each GPU, we need to take this offset into account. This including on setting up GPUVM page table and GART table v2: squash in "drm/amdgpu: Init correct fb region for none XGMI configuration" Acked-by:
Slava Abramov <slava.abramov@amd.com> Signed-off-by:
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Alex Deucher authored
Used to populate the xgmi info on vega20. v2: PF_MAX_REGION is val - 1 (Ray) Acked-by:
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Alex Deucher authored
Initial pass at a structure to store xgmi info. xgmi is a high speed cross gpu interconnect. Acked-by:
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Shaoyun Liu authored
Correct the definition based on vega20 register spec Signed-off-by:
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Emily Deng authored
since we use PSP to program IH regs now Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Acked-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Christian König authored
Otherwise we might run into a use after free during bulk move. Signed-off-by:
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Tao Zhou authored
Fix SDMA hang in prt mode, clear XNACK_WATERMARK in reg SDMA0_UTCL1_WATERMK to avoid the issue Affected ASICs: VEGA10 VEGA12 RV1 RV2 v2: add reg clear for SDMA1 Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Tested-by:
Yukun Li <yukun1.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Evan Quan authored
do_div expects the 1st argument in 64bit instead of 32bit. Drop the usage of do_div as it seems unnecessary. V2: drop usage of do_div completely Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Masanari Iida authored
This patch fixes following warnings. ./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:3011: warning: Excess function parameter 'dev' description in 'amdgpu_vm_get_task_info' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:3012: warning: Function parameter or member 'adev' not described in 'amdgpu_vm_get_task_info' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:3012: warning: Excess function parameter 'dev' description in 'amdgpu_vm_get_task_info' Signed-off-by:
Masanari Iida <standby24x7@gmail.com> Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Felix Kuehling authored
The intent of two commits was lost in the last rebase: 810955ba drm/amdgpu: Fix acquiring VM on large-BAR systems b5d21aac drm/amdgpu: Don't use shadow BO for compute context This commit restores the original behaviour: * Don't set AMDGPU_GEM_CREATE_NO_CPU_ACCESS for page directories to allow them to be reused for compute VMs * Don't create shadow BOs for page tables in compute VMs v2: move more logic into amdgpu_vm_bo_param Signed-off-by:
Kent Russell <Kent.Russell@amd.com> Reviewed-by:
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Christian König authored
Enable the old AGP aperture to avoid GART mappings. v2: don't enable it for SRIOV Signed-off-by:
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Felix Kuehling authored
Only initialize KFD once by moving amdgpu_amdkfd_init from amdgpu_pci_probe to amdgpu_init. This fixes kernel oopses and hangs when booting multi-GPU systems. Also removed some vestiges of KFD being its own module. Signed-off-by:
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Jun Lei authored
Existing debug dump are all invariant, new “low 32-bit of address” dump is not invariant Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Chiawen Huang authored
[Why] There are same purpose transition events. [How] remove the redundant event log. Signed-off-by:
Chiawen Huang <chiawen.huang@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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David Francis authored
[Why] The extraneous call to amdgpu_pm_compute_clocks is deprecated. [How] Remove it. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
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Eric Yang authored
[Why] Virtual sink is used when set mode happens on a disconnected display to allow the mode set to proceed. This did not work with MST because the logic for acquiring stream encoder uses stream signal to determine the special handling is required, and stream signal is virtual instead of DP in this case. [How] Use link type to decide instead. Signed-off-by:
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Tony Cheng authored
Signed-off-by:
Steven Chiu <Steven.Chiu@amd.com> Acked-by:
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David Francis authored
[Why] The i2c and aux engines are similar, and should be placed next to eachother for readability [How] Reorder the elements of the resource_pool struct Signed-off-by:
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Leo Li authored
[Why] Our implementation is functionally identical to DRM's Note that instead of checking if the provided id is 0, the helper follows through with the mode object search. However, It will still return NULL, since 0 is not a valid object id, and missed searches will return NULL. [How] Remove our implementation, and replace it with drm_atomic_helper_best_encoder. Signed-off-by:
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Hersen Wu authored
[why] AMD Stoney reference board, there are only 2 pipes (not include underlay), and 3 connectors. resource creation, only 2 I2C/AUX engines are created. Within dc_link_aux_transfer, when pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL. NULL point is referred later causing system crash. [how] each asic design has fixed number of ddc engines at hw side. for each ddc engine, create its i2x/aux engine at sw side. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Chiawen Huang authored
[Why] Enhance aux transition debugging information. [How] Added Aux request and reply event log. Signed-off-by:
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Derek Lai authored
Some display need disconnect delay. Adding this parameter for future use Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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