- 21 Jan, 2015 35 commits
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Hans de Goede authored
The a23-ippo-q8h tablets have volume up/down buttons using the lradc. This has been tested on both a v5 and a v1.2 tablet. Tested-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
The A23 has the same lradc controller as previous Allwinner SoCs. Signed-off-by:
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Chen-Yu Tsai authored
This patch adds the regulator nodes for the axp209 by including the axp209 dtsi. As the inputs of these regulators are from the axp209's PS output, which is basically just a mux over the 2 inputs, it is considered to be unregulated. Thus we do not provide input supply properties for them. The regulator names and constraints are based on the board schematics and the SoC datasheet. DCDC2 is used as the cpu power supply. This patch also references it from the cpu node. Also get rid of axp209 properties already set in axp209.dtsi. Signed-off-by:
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Chen-Yu Tsai authored
This patch adds the regulator nodes for the axp209 by including the axp209 dtsi. As the inputs of these regulators are from the axp209's PS output, which is basically just a mux over the 2 inputs, it is considered to be unregulated. Thus we do not provide input supply properties for them. The regulator names and constraints are based on the board schematics and the SoC datasheet. DCDC2 is used as the cpu power supply. This patch also references it from the cpu node. LDO3 powers the USB WiFi module. This patch also references it from the usb-phy node. Also get rid of axp209 properties already set in axp209.dtsi. Signed-off-by:
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Chen-Yu Tsai authored
This patch adds the regulator nodes for the axp209 by including the axp209 dtsi. As the inputs of these regulators are from the axp209's PS output, which is basically just a mux over the 2 inputs, it is considered to be unregulated. Thus we do not provide input supply properties for them. The regulator names and constraints are based on the board schematics and the SoC datasheet. DCDC2 is used as the cpu power supply. This patch also references it from the cpu node. Also get rid of axp209 properties already set in axp209.dtsi. Signed-off-by:
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Chen-Yu Tsai authored
This patch adds the regulator nodes for the axp209 by including the axp209 dtsi. As the inputs of these regulators are from the axp209's PS output, which is basically just a mux over the 2 inputs, it is considered to be unregulated. Thus we do not provide input supply properties for them. The regulator names and constraints are based on the board schematics and the SoC datasheet. DCDC2 is used as the cpu power supply. This patch also references it from the cpu node. Also get rid of axp209 properties already set in axp209.dtsi. Signed-off-by:
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Chen-Yu Tsai authored
The core temperature sensor now supports thermal zones. Add a thermal zone mapping for the cpus with passive cooling (cpufreq throttling). Signed-off-by:
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Chen-Yu Tsai authored
The core temperature sensor now supports thermal zones. Add a thermal zone mapping for the cpus with passive cooling (cpufreq throttling). Signed-off-by:
Eduardo Valentin <edubezval@gmail.com> Signed-off-by:
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Chen-Yu Tsai authored
The core temperature sensor now supports thermal zones. Add a thermal zone mapping for the cpus with passive cooling (cpufreq throttling). Signed-off-by:
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Chen-Yu Tsai authored
The AXP209 PMIC is used with some Allwinner SoCs. This patch adds a dtsi file listing all the regulator nodes. The regulators are initialized based on their device node names. Signed-off-by:
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Zoltan HERPAI authored
The pcDuino board has LEDs connected to PH15/PH16, and back/home/menu buttons to PH17/18/19 respectively. Enable these via gpio-leds and gpio-keys. This is shared across the v1 and v2 versions of the board. Tested on a v2 and verified against the schematics of a v1. Signed-off-by:
Zoltan HERPAI <wigyori@uid0.hu> Acked-by:
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Hans de Goede authored
Add simplefb nodes for "[de_fe0-]de_be0-lcd0" and "[de_fe0-]de_be0-lcd0-tve0" display pipelines for when u-boot has set up a pipeline to drive a LCD panel / VGA output rather then the HDMI output. Signed-off-by:
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Chen-Yu Tsai authored
The cpu core is clocked from the "cpu" clock. Add a reference to it in the first cpu node. Also add "cpu0" label to the node. The operating points were taken from the A10 FEX files in the sunxi-boards repository. All FEX files have the same settings. Signed-off-by:
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Chen-Yu Tsai authored
The cpu core is clocked from the "cpu" clock. Add a reference to it in the first cpu node. Also add "cpu0" label to the node. The operating points were taken from the A13 FEX files in the sunxi-boards repository. All FEX files have the same settings. Signed-off-by:
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Chen-Yu Tsai authored
The cpu core is clocked from the "cpu" clock. Add a reference to it in the first cpu node. Also add "cpu0" label to the node. The operating points were taken from the A20 FEX files in the sunxi-boards repository. Not all boards have the same settings. The settings in this patch are the most generic ones. Signed-off-by:
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Chen-Yu Tsai authored
Now that the resistive touchpanel driver supports thermal sensors, add the "#thermal-sensor-cells" property as required by the thermal framework. Signed-off-by:
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Maxime Ripard authored
The NMI IRQ controller uses the standard flags definition for the IRQ level and edges. Use the common header to use defines instead of opaque numbers. Signed-off-by: -
Maxime Ripard authored
The GIC requires some extra opaque arguments to set the IRQ type and flags. Convert the DTs to using the common defines. Signed-off-by: -
Maxime Ripard authored
The pinctrl nodes require some extra opaque arguments for the pull up and drive strength values. Introduce a new header file and convert the device trees to replace these opaque numbers by defines. Signed-off-by: -
Maxime Ripard authored
The DMA engine for the A10/A20 and derivatives require an opaque extra argument. Add a dt-bindings header, and convert the device trees to it. Signed-off-by: -
Maxime Ripard authored
Replace the various raw GPIO flags by their definition in the common dt-bindings header. Signed-off-by: -
Maxime Ripard authored
Prepare the device trees to use the C preprocessor. Signed-off-by: -
Hans de Goede authored
The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND, rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG controller), ethernet, 3.5 mm jack with a/v out and hdmi out. Note it has no sdcard slot and therefore can only be fel booted. Signed-off-by:
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Hans de Goede authored
Add a dtsi file for A31s based boards. Since the A31s is the same die as the A31 in a different package, this dtsi simply includes sun6i-a31.dtsi and then overrides the pinctrl compatible to reflect the different package, everything else is identical. Signed-off-by:
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Hans de Goede authored
Signed-off-by:
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Hans de Goede authored
Signed-off-by:
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Hans de Goede authored
Signed-off-by:
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Hans de Goede authored
The Mele M9 has an ir receiver, enable it. Signed-off-by:
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Hans de Goede authored
Add a node for the ir receiver found on the A31. Signed-off-by:
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Hans de Goede authored
Add an ir_clk sub-node to the prcm node. Signed-off-by:
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Alexandru Gagniuc authored
Only SPI0 is enabled, as the schematic denotes it as the only SPI bus, while other pins are reserved for different peripherals. Signed-off-by:
Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by:
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Alexandru Gagniuc authored
These are based on the available SPI configurations of Cubieboard, Olimex LIME, and PcDuino. There is no pin group for SPI3, as all the boards seem to use those pins for EMAC. Signed-off-by:
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Chen-Yu Tsai authored
On the Hummingbird A31 board, the RTL8211E ethernet phy has its reset line connect to a gpio pin, instead of floating like on other boards. Add the stmmac properties for describing the reset gpio. The reset delays were taken from the RTL8211E datasheet. Signed-off-by:
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Hans de Goede authored
Add pinmux settings for the ir receive pin of the A31. Signed-off-by:
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Hans de Goede authored
Testing has shown that on sun4i the display backend engine does not have deep enough fifo-s causing flickering / tearing in full-hd mode due to fifo underruns. This can be avoided by letting the display frontend engine do the dma from memory, and then letting it feed the data directly into the backend unmodified, as the frontend does have deep enough fifo-s. Note since u-boot-v2015.01 has been released using the de_be0-lcd0-hdmi pipeline on sun4i, we need to keep that one around too (unfortunately). Signed-off-by:
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- 06 Jan, 2015 1 commit
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Hans de Goede authored
The Ippo q8h has its serial console connected to the r-uart. Adjust the serial0 alias to match. This fixes the kernel serial console no longer working since 3.19-rc1, because 8250_dw.c now honors dt aliases, causing the serial console to be ttyS5 rather then being ttyS0, as it was in 3.18 and before. Note that adjusting bootargs instead is not an acceptable fix, because console=ttyS0,115200 is used by a lot of bootscripts, etc. and this should continue to work. Signed-off-by:
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- 21 Dec, 2014 4 commits
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Chen-Yu Tsai authored
usbphy0 support in the sunxi usb-phy driver has been merged, but the dtsi's for sun4i/sun5i haven't been updated. This results in the phy driver failing to load, breaking usb support. Fixes: 6827a46f ('phy: sun4i: add support for USB phy0') Signed-off-by:
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linuxLinus Torvalds authored
Pull ACCESS_ONCE cleanup preparation from Christian Borntraeger: "kernel: Provide READ_ONCE and ASSIGN_ONCE As discussed on LKML http://marc.info/?i=54611D86.4040306%40de.ibm.com ACCESS_ONCE might fail with specific compilers for non-scalar accesses. Here is a set of patches to tackle that problem. The first patch introduce READ_ONCE and ASSIGN_ONCE. If the data structure is larger than the machine word size memcpy is used and a warning is emitted. The next patches fix up several in-tree users of ACCESS_ONCE on non-scalar types. This does not yet contain a patch that forces ACCESS_ONCE to work only on scalar types. This is targetted for the next merge window as Linux next already contains new offenders regarding ACCESS_ONCE vs. non-scalar types" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux: s390/kvm: REPLACE barrier fixup with READ_ONCE arm/spinlock: Replace ACCESS_ONCE with READ_ONCE arm64/spinlock: Replace ACCESS_ONCE READ_ONCE mips/gup: Replace ACCESS_ONCE with READ_ONCE x86/gup: Replace ACCESS_ONCE with READ_ONCE x86/spinlock: Replace ACCESS_ONCE with READ_ONCE mm: replace ACCESS_ONCE with READ_ONCE or barriers kernel: Provide READ_ONCE and ASSIGN_ONCE
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git://git.linaro.org/people/mike.turquette/linuxLinus Torvalds authored
Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
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