- 08 Aug, 2016 40 commits
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Emily Deng authored
For virtual display feature, add one connector type in amdgpu_connector_add. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Emily Deng authored
For virtual display feature, as there is no dce engine, so no pageflip irq generated. So directly call pageflip irq funtion when received vysn interrupt. Signed-off-by:
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Emily Deng authored
For virtual display feature, use the software timer to simulate the vsync interrupt. Signed-off-by:
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Emily Deng authored
For virtual display feature, when the GPU has DCE engine, need to disable the VGA render and CRTC, or it will hang when initialize GMC. Signed-off-by:
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Emily Deng authored
For virtual display feature, when the GPU has DCE engine, need to disable the VGA render and CRTC, or it will hang when initialize GMC. So first detect whether the GPU has DCE engine. Signed-off-by:
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Emily Deng authored
For virtual display feature, initialize dce_virtual_crtc_funcs. v2: agd: rebase on upstream Signed-off-by:
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Emily Deng authored
For virtual display feature, initialize dce_virtual_crtc_helper_funcs. Signed-off-by:
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Emily Deng authored
For virtual display feature, initialize dce_virtual_crtc_irq_funcs, dce_virtual_pageflip_irq_funcs. As it has no dce engine, so the pageflip interrupt won't be generated, and the vsync interrupt will be generated by smu's periodic timer or software timer which will be implemented later. v2: agd: rebase on upstream Signed-off-by:
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Emily Deng authored
For virtual display feature, initialize dce_virtual_display_funcs, which will be used in function dce_virtual_set_display_funcs. Signed-off-by:
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Emily Deng authored
For virtual display feature, first need to initialize dce_virtual_ip_funcs, which will be used when set ip blocks. Signed-off-by:
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Emily Deng authored
For virtual display feature, add virtual connector and encoder macros. Signed-off-by:
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Lyude authored
When this code was written, we didn't retry DP aux transactions on any error, which required retrying important transactions like this in individual drivers. Since that's no longer the case, retrying here is not necessary. As well, we retry any aux transaction on any error 32 times. 7 * 32 = 224, which means this loop causes us to retry grabbing the dpcd 224 times. This is definitely far more then we actually need to do. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Lyude <cpaul@redhat.com> Signed-off-by:
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Lyude authored
Since it's normal for DRM to retry our aux transaction helpers multiple times in a row, up to 32 times for each attempted transaction, we're making a lot of noise that is no longer necessary now that DRM will just print the return code we give it. Reviewed-by:
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Lyude authored
When this code was written, we didn't retry DP aux transactions on any error, which required retrying important transactions like this in individual drivers. Since that's no longer the case, retrying here is not necessary. As well, we retry any aux transaction on any error 32 times. 7 * 32 = 224, which means this loop causes us to retry grabbing the dpcd 224 times. This is definitely far more then we actually need to do. Reviewed-by:
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Lyude authored
Since it's normal for DRM to retry our aux transaction helpers multiple times in a row, up to 32 times for each attempted transaction, we're making a lot of noise that is no longer necessary now that DRM will just print the return code we give it. Reviewed-by:
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Michel Dänzer authored
Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Michel Dänzer authored
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Michel Dänzer authored
Fixes hangs under memory pressure, e.g. running the piglit test tex3d-maxsize concurrently with other tests. Fixes: 17d33bc9 ("drm/ttm: drop waiting for idle in ttm_bo_evict.") Reviewed-by:
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Alex Deucher authored
For consistency. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Huang Rui authored
Enable powerplay as default on Carrizo and Stoney. And it can be disabled with amdgpu.powerplay=0. Reviewed-by:
Huang Rui <ray.huang@amd.com> Cc: Rex Zhu <Rex.Zhu@amd.com> Cc: Flora Cui <Flora.Cui@amd.com> Cc: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by:
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Rex Zhu authored
Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
they were controled by module parameter. Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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Rex Zhu authored
This is a workaround to let VCE soft reset work. RB1_BUSY bit is always set, so remove its checking now, and we will depend on RB0_BUSY currently. After we find the root cause of RB1_BUSY, we can add it back. Signed-off-by:
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Chunming Zhou authored
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Chunming Zhou authored
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Tom St Denis authored
Partially undo changes made by commit: drm/amd/amdgpu: don't track state in UVD clockgating To keep bypass even if CG flags are not set. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
It's handled by DPM/PP properly. Signed-off-by:
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Tom St Denis authored
CG was being enabled in reverse sense from dpm/powerplay. Also fix the default CLK_EN signal to enable all of the blocks. Signed-off-by:
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Tom St Denis authored
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Leo Liu authored
This will make clock and power gated when no block decoded, for example when paused during the playback. Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Marek Olšák authored
It's useful for debugging. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Ken Wang authored
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Ken Wang authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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