- 27 Mar, 2020 40 commits
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David S. Miller authored
Igor Russkikh says: ==================== net: atlantic: MACSec support for AQC devices This patchset introduces MACSec HW offloading support in Marvell(Aquantia) AQC atlantic driver. This implementation is a joint effort of Marvell developers on top of the work started by Antoine Tenart. v2: * clean up the generated code (removed useless bit operations); * use WARN_ONCE to avoid log spam; * use put_unaligned_be64; * removed trailing \0 and length limit for format strings; v1: https://patchwork.ozlabs.org/cover/1259998/ RFC v2: https://patchwork.ozlabs.org/cover/1252204/ RFC v1: https://patchwork.ozlabs.org/cover/1238082/ Several patches introduce backward-incompatible changes and are subject for discussion/drop: 1) patch 0007: multicast/broadcast when offloading is needed to handle ARP requests, because they have broadcast destination address; With this patch we also match and encrypt/decrypt packets between macsec hw and realdev based on device's mac address. This can potentially be used to support multiple macsec offloaded interfaces on top of one realdev. However in some environments this could lead to problems, e.g. the 'bridge over macsec' configuration will expect the packets with unknown src MAC should come through macsec. The patch is questionable, we've used it because our current hw setup and requirements both assume that the decryption is done based on mac address match only. This could be changed by encrypting/decripting all the traffic (except control). 2) patch 0009: real_dev features are now propagated to macsec device (when HW offloading is enabled), otherwise feature set might lead to HW reconfiguration during MACSec configuration. Also, HW offloaded macsec should be able to keep LRO LSO features, since they are transparent for macsec engine (at least in our hardware). ==================== Signed-off-by:
David S. Miller <davem@davemloft.net>
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Mark Starovoytov authored
This patch adds XPN handling. Our driver doesn't support XPN, but we should still update a couple of places in the code, because the size of 'next_pn' field has changed. Signed-off-by:
Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by:
Igor Russkikh <irusskikh@marvell.com> Signed-off-by:
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Dmitry Bogdanov authored
This patch adds support for MACSec statistics on Atlantic network cards. Signed-off-by:
Dmitry Bogdanov <dbogdanov@marvell.com> Signed-off-by:
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Dmitry Bogdanov authored
This patch adds the Atlantic HW-specific bindings for MACSec statistics, e.g. register addresses / structs, helper function, etc, which will be used by actual callback implementations. Signed-off-by:
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Mark Starovoytov authored
This patch adds support for MACSec ingress HW offloading on Atlantic network cards. Signed-off-by:
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Mark Starovoytov authored
This patch adds the Atlantic HW-specific bindings for MACSec ingress, e.g. register addresses / structs, helper function, etc, which will be used by actual callback implementations. Signed-off-by:
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Dmitry Bogdanov authored
This patch adds support for MACSec egress HW offloading on Atlantic network cards. Signed-off-by:
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Dmitry Bogdanov authored
This patch adds the Atlantic HW-specific bindings for MACSec egress, e.g. register addresses / structs, helper function, etc, which will be used by actual callback implementations. Signed-off-by:
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Dmitry Bogdanov authored
This patch adds basic functionality for MACSec offloading for Atlantic NICs. MACSec offloading functionality is enabled if network card has appropriate FW that has MACSec offloading enabled in config. Actual functionality (ingress, egress, etc) will be added in follow-up patches. Signed-off-by:
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Mark Starovoytov authored
This patch makes real_dev_feature propagation by MACSec offloaded device. Issue description: real_dev features are disabled upon macsec creation. Root cause: Features limitation (specific to SW MACSec limitation) is being applied to HW offloaded case as well. This causes 'set_features' request on the real_dev with reduced feature set due to chain propagation. Proposed solution: Report real_dev features when HW offloading is enabled. NB! MACSec offloaded device does not propagate VLAN offload features at the moment. This can potentially be added later on as a separate patch. Note: this patch requires HW offloading to be enabled by default in order to function properly. Signed-off-by:
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Dmitry Bogdanov authored
When HW offloading is enabled, offloaded stats should be used, because s/w stats are wrong and out of sync with the HW in this case. Signed-off-by:
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Mark Starovoytov authored
The idea is simple. If the frame is an exact match for the controlled port (based on DA comparison), then we simply divert this skb to matching port. Multicast/broadcast messages are delivered to all ports. Signed-off-by:
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Dmitry Bogdanov authored
Offload engine can setup several SecY. Each macsec interface shall have its own mac address. It will filter a traffic by dest mac address. Signed-off-by:
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Dmitry Bogdanov authored
This patch adds secy pointer initialization in the macsec_context. It will be used by MAC drivers in offloading operations. Signed-off-by:
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Antoine Tenart authored
This patch adds a new MACsec offloading option, MACSEC_OFFLOAD_MAC, allowing a user to select a MAC as a provider for MACsec offloading operations. Signed-off-by:
Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by:
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Antoine Tenart authored
This patch allows to reference a net_device from a MACsec context. This is needed to allow implementing MACsec operations in net device drivers. Signed-off-by:
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Antoine Tenart authored
This patch adds a reference to MACsec ops to the net_device structure, allowing net device drivers to implement offloading operations for MACsec. Signed-off-by:
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Antoine Tenart authored
This patch introduce a new netdev feature, which will be used by drivers to state they can perform MACsec transformations in hardware. The patchset was gathered by Mark, macsec functinality itself was implemented by Dmitry, Mark and Pavel Belous. Signed-off-by:
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Eugene Syromiatnikov authored
BIT() macro definition is internal to the Linux kernel and is not to be used in UAPI headers; replace its usage with the _BITUL() macro that is already used elsewhere in the header. Fixes: 9c66d156 ("taprio: Add support for hardware offloading") Signed-off-by:
Eugene Syromiatnikov <esyr@redhat.com> Acked-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by:
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Maciej Żenczykowski authored
This is trivial since we already have support for the entirely identical (from the kernel's point of view) RDNSS, DNSSL, etc. that also contain opaque data that needs to be passed down to userspace for further processing. As specified in draft-ietf-6man-ra-pref64-09 (while it is still a draft, it is purely waiting on the RFC Editor for cleanups and publishing): PREF64 option contains lifetime and a (up to) 96-bit IPv6 prefix. The 8-bit identifier of the option type as assigned by the IANA is 38. Since we lack DNS64/NAT64/CLAT support in kernel at the moment, thus this option should also be passed on to userland. See: https://tools.ietf.org/html/draft-ietf-6man-ra-pref64-09 https://www.iana.org/assignments/icmpv6-parameters/icmpv6-parameters.xhtml#icmpv6-parameters-5 Cc: Erik Kline <ek@google.com> Cc: Jen Linkova <furry@google.com> Cc: Lorenzo Colitti <lorenzo@google.com> Cc: Michael Haro <mharo@google.com> Signed-off-by:
Maciej Żenczykowski <maze@google.com> Acked-By:
Lorenzo Colitti <lorenzo@google.com> Signed-off-by:
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David S. Miller authored
Grygorii Strashko says: ==================== net: ethernet: ti: add networking support for k3 am65x/j721e soc This v6 series adds basic networking support support TI K3 AM654x/J721E SoC which have integrated Gigabit Ethernet MAC (Media Access Controller) into device MCU domain and named MCU_CPSW0 (CPSW2G NUSS). Formally TRMs refer CPSW2G NUSS as two-port Gigabit Ethernet Switch subsystem with port 0 being the CPPI DMA host port and port 1 being the external Ethernet port, but for 1 external port device it's just Port 0 <-> ALE <-> Port 1 and it's rather device with HW filtering capabilities then actually switching device. It's expected to have similar devices, but with more external ports. The new Host port 0 Communications Port Programming Interface (CPPI5) is operating by TI AM654x/J721E NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller [1]. The CPSW2G contains below modules for which existing code is re-used: - MAC SL: cpsw_sl.c - Address Lookup Engine (ALE): cpsw_ale.c, basically compatible with K2 66AK2E/G - Management Data Input/Output interface (MDIO): davinci_mdio.c, fully compatible with TI AM3/4/5 devices Basic features supported by CPSW2G NUSS driver: - VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on ingress, Auto VLAN removal on egress and auto pad to minimum frame size. - multicast filtering - promisc mode - TX multiq support in Round Robin or Fixed priority modes - RX checksum offload for non-fragmented IPv4/IPv6 TCP/UDP packets - TX checksum offload support for IPv4/IPv6 TCP/UDP packets (J721E only). Features under development: - Support for IEEE 1588 Clock Synchronization. The CPSW2G NUSS includes new version of Common Platform Time Sync (CPTS) - tc-mqprio: priority level Quality Of Service (QOS) support (802.1p) - tc-cbs: Support for Audio/Video Bridging (P802.1Qav/D6.0) HW shapers - tc-taprio: IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic - frame preemption: IEEE P902.3br/D2.0 Interspersing Express Traffic, 802.1Qbu - extended ALE features: classifier/policers, auto-aging Patches 1-6 are intended for netdev, Patches 7-11 are intended for K3 Platform tree and provided here for testing purposes. Changes in v6: - fixed comments from Rob Herring <robh@kernel.org> and added his Reviewed-by. - added Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Changes in v5: - renamed files k3-udma-desc-pool.* k3-udma-desc-pool to k3-cppi-desc-pool.*, and API to k3_cppi_desc_pool_* as requested by Peter Ujfalusi <peter.ujfalusi@ti.com> - fixed copy-paste err in am65_cpsw_nuss_ndo_slave_set_rx_mode() which blocked recieving of mcast frames. - added Tested-by: Murali Karicheri <m-karicheri2@ti.com> Changes in v4: - fixed minor comments from Jakub Kicinski <kuba@kernel.org> - dependencies resolved: required phy-rmii-sel changes [2] queued for merge except one [3] which is included in this series with Kishon's ask. Changes in v3: - add ARM64 defconfig changes for testing purposes - fixed DT yaml definition - fixed comments from Jakub Kicinski <kuba@kernel.org> Changes in v2: - fixed DT yaml definition - fixed comments from David Miller v5: https://patchwork.ozlabs.org/cover/1258295/ v4: https://patchwork.ozlabs.org/cover/1256092/ v3: https://patchwork.ozlabs.org/cover/1254568/ v2: https://patchwork.ozlabs.org/cover/1250674/ v1: https://lwn.net/Articles/813087/ TRMs: AM654: http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf J721E: http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf Preliminary documentation can be found at: http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/K3_CPSW2g.html [1] https://lwn.net/Articles/808030/ [2] https://lkml.org/lkml/2020/2/22/100 [3] https://lkml.org/lkml/2020/3/3/724 ==================== Signed-off-by:
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Grygorii Strashko authored
Enable TI K3 AM654x/J721E DMA and networking options. Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Tested-by:
Murali Karicheri <m-karicheri2@ti.com> Tested-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
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Grygorii Strashko authored
The TI J721E EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI j721e SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by:
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Grygorii Strashko authored
Add DT node for The TI J721E MCU SoC Gigabit Ethernet subsystem (MCU CPSW NUSS). Signed-off-by:
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Grygorii Strashko authored
AM654 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI am654 SoC Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by:
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Grygorii Strashko authored
Add DT node for the TI AM65x SoC Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by:
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Grygorii Strashko authored
The TI AM65x/J721E SoCs Gigabit Ethernet Switch subsystem (CPSW2G NUSS) has two ports - One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0) and with ALE in between. It also contains - Management Data Input/Output (MDIO) interface for physical layer device (PHY) management; - Updated Address Lookup Engine (ALE) module; - (TBD) New version of Common platform time sync (CPTS) module. On the TI am65x/J721E SoCs CPSW NUSS Ethernet subsystem into device MCU domain named MCU_CPSW0. Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and one RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Introduced driver provides standard Linux net_device to user space and supports: - ifconfig up/down - MAC address configuration - ethtool operation: --driver --change --register-dump --negotiate phy --statistics --set-eee phy --show-ring --show-channels --set-channels - net_device ioctl mii-control - promisc mode - rx checksum offload for non-fragmented IPv4/IPv6 TCP/UDP packets. The CPSW NUSS can verify IPv4/IPv6 TCP/UDP packets checksum and fills csum information for each packet in psdata[2] word: - BIT(16) CHECKSUM_ERROR - indicates csum error - BIT(17) FRAGMENT - indicates fragmented packet - BIT(18) TCP_UDP_N - Indicates TCP packet was detected - BIT(19) IPV6_VALID, BIT(20) IPV4_VALID - indicates IPv6/IPv4 packet - BIT(15, 0) CHECKSUM_ADD - This is the value that was summed during the checksum computation. This value is FFFFh for non fragmented IPV4/6 UDP/TCP packets with no checksum error. RX csum offload can be disabled: ethtool -K <dev> rx-checksum on|off - tx checksum offload support for IPv4/IPv6 TCP/UDP packets (J721E only). TX csum HW offload can be enabled/disabled: ethtool -K <dev> tx-checksum-ip-generic on|off - multiq and switch between round robin/prio modes for cppi tx queues by using Netdev private flag "p0-rx-ptype-rrobin" to switch between Round Robin and Fixed priority modes: # ethtool --show-priv-flags eth0 Private flags for eth0: p0-rx-ptype-rrobin: on # ethtool --set-priv-flags eth0 p0-rx-ptype-rrobin off Number of TX DMA channels can be changed using "ethtool -L eth0 tx <N>". - GRO support: the napi_gro_receive() and napi_complete_done() are used. Signed-off-by:
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Grygorii Strashko authored
Document device tree bindings for The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller - CPSW2G NUSS). The CPSW NUSS provides Ethernet packet communication for the device. Signed-off-by:
Rob Herring <robh@kernel.org> Tested-by:
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Grygorii Strashko authored
Add support for default thread configuration for AM65x CPSW NUSS ALE to allow route all ingress packets to one default RX UDMA flow. Signed-off-by:
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Grygorii Strashko authored
The new CPSW ALE version, available on TI K3 AM654/J721E SoCs family, allows to switch any external port to MAC only mode. When MAC only mode enabled this port be treated like a MAC port for the host. All traffic received is only sent to the host. The host must direct traffic to this port as the lookup engine will not send traffic to the ports with the p0_maconly bit set and the p0_no_learn also set. If p0_maconly bit is set and the p0_no_learn is not set, the host can send non-directed packets that can be sent to the destination of a MacOnly port. It is also possible that The host can broadcast to all ports including MacOnly ports in this mode. This patch add ALE supprt for MAC only mode. Signed-off-by:
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Grygorii Strashko authored
On AM65xx MCU CPSW2G NUSS and 66AK2E/L NUSS the unregistered multicast packets are still can be received with promisc and allmulti disabled. This happens, because ALE VLAN entries on these SoCs do not contain port masks for reg/unreg mcast packets, but instead store indexes of ALE_VLAN_MASK_MUXx_REG registers which intended for store port masks for reg/unreg mcast packets. ALE VLAN entry:UNREG_MCAST_FLOOD_INDEX -> ALE_VLAN_MASK_MUXx ALE VLAN entry:REG_MCAST_FLOOD_INDEX -> ALE_VLAN_MASK_MUXy The commit b361da83 ("net: netcp: ale: add proper ale entry mask bits for netcp switch ALE") update ALE code to support such ALE entries, it is always used ALE_VLAN_MASK_MUX0_REG index in ALE VLAN entry for unreg mcast packets mask configuration, which is read-only, at least for AM65xx MCU CPSW2G NUSS and 66AK2E/L NUSS. As result unreg mcast packets are allowed always. Hence, update ALE code to use ALE_VLAN_MASK_MUX1_REG index for ALE VLAN entries to configure unreg mcast port mask. Fixes: b361da83 ("net: netcp: ale: add proper ale entry mask bits for netcp switch ALE") Signed-off-by:
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Grygorii Strashko authored
The phy-gmii-sel can be only auto selected in Kconfig and now the pretty complex Kconfig dependencies are defined for phy-gmii-sel driver, which also need to be updated every time phy-gmii-sel is re-used for any new networking driver. Simplify Kconfig definition for phy-gmii-sel PHY driver - drop all dependencies and from networking drivers and rely on using 'imply PHY_TI_GMII_SEL' in Kconfig definitions for networking drivers instead. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Tested-by:
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David S. Miller authored
Guillaume Nault says: ==================== cls_flower: Use extack in fl_set_key() Add missing extack messages in fl_set_key(), so that users can get more meaningfull error messages when netlink attributes are rejected. Patch 1 also extends extack in tcf_change_indev() (in pkt_cls.h) since this function is used by fl_set_key(). ==================== Signed-off-by: -
Guillaume Nault authored
Pass extack down to fl_set_key_flags() and set message on error. Signed-off-by:
Guillaume Nault <gnault@redhat.com> Signed-off-by:
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Guillaume Nault authored
Pass extack down to fl_set_key_port_range() and set message on error. Both the min and max ports would qualify as invalid attributes here. Report the min one as invalid, as it's probably what makes the most sense from a user point of view. Signed-off-by:
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Guillaume Nault authored
Pass extack down to fl_set_key_mpls() and set message on error. Signed-off-by:
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Guillaume Nault authored
Add an error message when device wasn't found. While there, also set the bad attribute's offset in extack. Signed-off-by:
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David S. Miller authored
Tobias Waldekranz says: ==================== net: phy: marvell usb to mdio controller Support for an MDIO controller present on development boards for Marvell switches from the Link Street (88E6xxx) family. v3->v4: - Remove unnecessary dependency on OF_MDIO. v2->v3: - Rename driver smi2usb -> mvusb. - Clean up unused USB references. v1->v2: - Reverse christmas tree ordering of local variables. ==================== Signed-off-by: -
Tobias Waldekranz authored
An MDIO controller present on development boards for Marvell switches from the Link Street (88E6xxx) family. Using this module, you can use the following setup as a development platform for switchdev and DSA related work. .-------. .-----------------. | USB----USB | | SoC | | 88E6390X-DB ETH1-10 | ETH----ETH0 | '-------' '-----------------' Signed-off-by:
Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Tobias Waldekranz authored
Describe how the USB to MDIO controller can optionally use device tree bindings to reference attached devices such as switches. Signed-off-by:
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