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  1. 30 May, 2014 2 commits
    • Maciej W. Rozycki's avatar
      MIPS: Implement random_get_entropy with CP0 Random · 06947aaa
      Maciej W. Rozycki authored
      Update to commit 9c9b415c [MIPS:
      Reimplement get_cycles().]
      
      On systems were for whatever reasons we can't use the cycle counter, fall
      back to the c0_random register as an entropy source.  It has however a
      very small range that makes it suitable for random_get_entropy only and
      not get_cycles.
      
      This optimised version compiles to 8 instructions in the fast path even in
      the worst case of all the conditions to check being variable (including a
      MFC0 move delay slot that is only required for very old processors):
      
           828:	8cf90000 	lw	t9,0(a3)
      			828: R_MIPS_LO16	jiffies
           82c:	40057800 	mfc0	a1,c0_prid
           830:	3c0200ff 	lui	v0,0xff
           834:	00a21024 	and	v0,a1,v0
           838:	1040007d 	beqz	v0,a30 <add_interrupt_randomness+0x22c>
           83c:	3c030000 	lui	v1,0x0
      			83c: R_MIPS_HI16	cpu_data
           840:	40024800 	mfc0	v0,c0_count
           844:	00000000 	nop
           848:	00409021 	move	s2,v0
           84c:	8ce20000 	lw	v0,0(a3)
      			84c: R_MIPS_LO16	jiffies
      
      On most targets the sequence will be shorter and on some it will reduce to
      a single `MFC0 <reg>,c0_count', as all MIPS architecture (i.e. non-legacy
      MIPS) processors require the CP0 Count register to be present.
      
      The only known exception that reports MIPS architecture compliance, but
      contrary to that lacks CP0 Count is the Ingenic JZ4740 thingy.  For broken
      platforms like that this code requires cpu_has_counter to be hardcoded to
      0 (i.e. no variable setting is permitted) so as not to penalise all the
      other good platforms out there.
      
      The asm barrier is required so that the compiler does not pull any
      potentially costly (cold cache!) `cpu_data' variable access into the fast
      path.
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
      Cc: Theodore Ts'o <tytso@mit.edu>
      Cc: John Crispin <blogic@openwrt.org>
      Cc: Andrew McGregor <andrewmcgr@gmail.com>
      Cc: Dave Taht <dave.taht@bufferbloat.net>
      Cc: Felix Fietkau <nbd@nbd.name>
      Cc: Simon Kelley <simon@thekelleys.org.uk>
      Cc: Jim Gettys <jg@freedesktop.org>
      Cc: David Daney <ddaney@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/6702/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      06947aaa
    • Yonghong Song's avatar
      MIPS: Netlogic: Add support for XLP5XX · 1c983986
      Yonghong Song authored
      Add support for the XLP5XX processor which is an 8 core variant of the
      XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX.
      Signed-off-by: default avatarYonghong Song <ysong@broadcom.com>
      Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/6871/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      1c983986
  2. 23 May, 2014 2 commits
  3. 31 Mar, 2014 3 commits
  4. 26 Mar, 2014 7 commits
  5. 06 Mar, 2014 1 commit
  6. 24 Jan, 2014 1 commit
  7. 22 Jan, 2014 5 commits
  8. 13 Jan, 2014 1 commit
    • Paul Burton's avatar
      MIPS: Support for 64-bit FP with O32 binaries · 597ce172
      Paul Burton authored
      CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs
      do. In order to preserve backwards compatibility a 64-bit FPU will act
      like a 32-bit FPU (by accessing doubles from the least significant 32
      bits of an even-odd pair of FP registers) when the Status.FR bit is
      zero, again just like a mips64 CPU. The standard O32 ABI is defined
      expecting a 32-bit FPU, however recent toolchains support use of a
      64-bit FPU from an O32 MIPS32 executable. When an ELF executable is
      built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF
      header.
      
      With this patch the kernel will check the EF_MIPS_FP64 flag when
      executing an O32 binary, and set Status.FR accordingly. The addition
      of O32 64-bit FP support lessens the opportunity for optimisation in
      the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is
      introduced to allow this support to be disabled for those that don't
      require it.
      
      Inspired by an earlier patch by Leonid Yegoshin, but implemented more
      cleanly & correctly.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Paul Burton <paul.burton@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/6154/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      597ce172
  9. 29 Oct, 2013 2 commits
  10. 19 Sep, 2013 1 commit
  11. 18 Sep, 2013 1 commit
  12. 17 Sep, 2013 1 commit
  13. 03 Sep, 2013 1 commit
  14. 26 Aug, 2013 1 commit
  15. 14 Jul, 2013 1 commit
    • Paul Gortmaker's avatar
      MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code · 078a55fc
      Paul Gortmaker authored
      commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
      
      The __cpuinit type of throwaway sections might have made sense
      some time ago when RAM was more constrained, but now the savings
      do not offset the cost and complications.  For example, the fix in
      commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
      is a good example of the nasty type of bugs that can be created
      with improper use of the various __init prefixes.
      
      After a discussion on LKML[1] it was decided that cpuinit should go
      the way of devinit and be phased out.  Once all the users are gone,
      we can then finally remove the macros themselves from linux/init.h.
      
      Note that some harmless section mismatch warnings may result, since
      notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
      and are flagged as __cpuinit  -- so if we remove the __cpuinit from
      the arch specific callers, we will also get section mismatch warnings.
      As an intermediate step, we intend to turn the linux/init.h cpuinit
      related content into no-ops as early as possible, since that will get
      rid of these warnings.  In any case, they are temporary and harmless.
      
      Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
      from asm files.  MIPS is interesting in this respect, because there
      are also uasm users hiding behind their own renamed versions of the
      __cpuinit macros.
      
      [1] https://lkml.org/lkml/2013/5/20/589
      
      [ralf@linux-mips.org: Folded in Paul's followup fix.]
      Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/5494/
      Patchwork: https://patchwork.linux-mips.org/patch/5495/
      Patchwork: https://patchwork.linux-mips.org/patch/5509/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      078a55fc
  16. 01 Jul, 2013 2 commits
    • Steven J. Hill's avatar
      MIPS: microMIPS: Fix improper definition of ISA exception bit. · c6213c6c
      Steven J. Hill authored
      The ISA exception bit selects whether exceptions are taken in classic
      or microMIPS mode. This bit is Config3.ISAOnExc and was improperly
      defined as bits 16 and 17 instead of just bit 16. A new function was
      added so that platforms could set this bit when running a kernel
      compiled with only microMIPS instructions.
      Signed-off-by: default avatarSteven J. Hill <Steven.Hill@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/5377/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      c6213c6c
    • Ralf Baechle's avatar
      MIPS: Get rid of MIPS I flag and test macros. · 1990e542
      Ralf Baechle authored
      MIPS I is the ancestor of all MIPS ISA and architecture variants.  Anything
      ever build in the MIPS empire is either MIPS I or at least contains MIPS I.
      If it's running Linux, that is.
      
      So there is little point in having cpu_has_mips_1 because it will always
      evaluate as true - though usually only at runtime.  Thus there is no
      point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it.
      
      Little complication: traps.c was using a test for a pure MIPS I ISA as
      a test for an R3000-style cp0.  To deal with that, use a check for
      cpu_has_3kex or cpu_has_4kex instead.
      
      cpu_has_3kex is a new macro.  At the moment its default implementation is
      !cpu_has_4kex but this may eventually change if Linux is ever going to
      support the oddball MIPS processors R6000 and R8000 so users of either
      of these macros should not make any assumptions.
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Patchwork: https://patchwork.linux-mips.org/patch/5551/
      1990e542
  17. 13 Jun, 2013 1 commit
  18. 21 May, 2013 1 commit
  19. 09 May, 2013 1 commit
  20. 05 Apr, 2013 1 commit
  21. 12 Mar, 2013 1 commit
  22. 19 Feb, 2013 1 commit
  23. 16 Feb, 2013 2 commits