- 04 Jan, 2020 1 commit
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Maxime Ripard authored
Some old SoCs, while supporting LVDS, don't list the LVDS clocks and reset lines. Let's add them when relevant. Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime@cerno.tech>
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- 03 Jan, 2020 3 commits
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Jagan Teki authored
tcon_tv0, tcon_tv1 nodes have a clock names of tcon-ch0, tcon-ch1 which are referring tcon_top clocks via index numbers like 0, 1 with CLK_TCON_TV0 and CLK_TCON_TV1 respectively. Use the macro in place of index numbers, for more code readability. Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Reviewed-by:
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Andre Przywara authored
The ARM Cortex-A7 cores used in the Allwinner R40 SoC have their usual Performance Monitoring Unit (PMU), which allows perf to use hardware events. The SoC integrator just needs to connect each per-core interrupt line to the GIC. The R40 manual does not really mention those IRQ lines, but experimentation in U-Boot shows that interrupts 152-155 are connected to the four cores (similar to the A20). Tested on a Bananapi M2 Berry, with perf and taskset to confirm the association between cores and interrupts. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Signed-off-by:
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Andre Przywara authored
The GIC used in the R40 SoC is an ARM GIC-400 with virtualization support, so let's advertise the full 8K region of the GICC MMIO frame to enable KVM's usage of the GIC (as we do already for all other SoCs). Tested by running KVM on a Bananapi M2 Berry. Signed-off-by:
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- 27 Dec, 2019 1 commit
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Ondrej Jirman authored
There are two sensors, one for CPU, one for GPU. Signed-off-by:
Ondrej Jirman <megous@megous.com> Signed-off-by:
Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by:
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- 26 Dec, 2019 6 commits
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Chen-Yu Tsai authored
The Libre Computer ALL-H3-IT board is a small single board computer that is roughly the same size as the Raspberry Pi Zero, or around 20% smaller than a credit card. The board features: - H2, H3, or H5 SoC from Allwinner - 2 DDR3 DRAM chips - Realtek RTL8821CU based WiFi module - 128 Mbit SPI-NOR flash - micro-SD card slot - micro HDMI video output - FPC connector for camera sensor module - generic Raspberri-Pi style 40 pin GPIO header - additional pin headers for extra USB host ports, ananlog audio and IR receiver Only H5 variant test samples were made available, but the vendor does have plans to include at least an H3 variant. Thus the device tree is split much like the ALL-H3-CC, with a common dtsi file for the board design, and separate dts files including the common board file and the SoC dtsi file. The other variants will be added as they are made available. Signed-off-by: -
Jagan Teki authored
Add MIPI DSI pipeline for Allwinner A64. - dsi node, with A64 compatible since it doesn't support DSI_SCLK gating unlike A33 - dphy node, with A64 compatible with A33 fallback since DPHY on A64 and A33 is similar - finally, attach the dsi_in to tcon0 for complete MIPI DSI Signed-off-by:
Merlijn Wajer <merlijn@wizzup.org> Signed-off-by:
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Vasily Khoruzhick authored
A64 has 3 thermal sensors: 1 for CPU, 2 for GPU. Signed-off-by:
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Ondrej Jirman authored
There are two sensors, one for CPU, one for GPU. Signed-off-by:
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Ondrej Jirman authored
There is just one sensor for the CPU. Signed-off-by:
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Ondrej Jirman authored
There are three sensors, two for each CPU cluster, one for GPU. Signed-off-by:
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- 20 Dec, 2019 5 commits
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Maxime Ripard authored
The MMC configuration clock controller in the A80 definition has a clock-names and reset-names property, even though the binding for that controller doesn't declare it. Remove it. Acked-by:
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Maxime Ripard authored
Even though it translates to the same thing down to the binary level, we should have an array of 2 number cells to describe each voltage state, which in turns create a validation warning. Let's fix this. Acked-by:
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Maxime Ripard authored
The TCON binding mandates a dmas phandle to the DMAengine channel used for that controller. However, since it's not used in the driver, some device trees have been missing it. Let's add it. Acked-by:
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Maxime Ripard authored
The V3s mixer node has an assigned clocks property, while the driver also enforces it. Since assigned-clocks is pretty fragile anyway, let's just remove it. Acked-by:
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Maxime Ripard authored
While this is functional, it's a best practice to always have the clocks and reset lines in order, in case we ever need to have compatibility code. Acked-by:
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- 16 Dec, 2019 7 commits
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Maxime Ripard authored
The Allwinner A80 SoC has a display clocks controller that is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Maxime Ripard authored
The Allwinner A80 SoC has a USB clocks controller that is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Reviewed-by:
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Maxime Ripard authored
The newer Allwinner SoCs have a DE2 clocks controller that is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Reviewed-by:
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Chen-Yu Tsai authored
The R40 has five I2C controllers. Currently only I2C0 has its pinmux option defined. Add the options for the remaining four, and set them as the default, since each controller has only one possible pinmux configuration. Signed-off-by:
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Clément Péron authored
Allwinner device tree files used different comment style for copyright notice. Update this to keep a coherency. Signed-off-by:
Clément Péron <peron.clem@gmail.com> Signed-off-by:
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Clément Péron authored
Use a shorter SPDX identifier instead of pasting the whole license. Signed-off-by:
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Clément Péron authored
Some headers specify that files are under dual-licensed GPL2.0+ and X11. But in fact, it turns out that the full licenses texts associated are GPL2.0+ and MIT. Fix license headers to reflect real licenses associated. Signed-off-by:
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- 11 Dec, 2019 4 commits
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Clément Péron authored
With dual licensed SPDX identifier the "OR" should be uppercase. Signed-off-by:
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Stefan Mavrodiev authored
Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL. This patch adds regulators for them to the pinctrl node. Exception is PL which is used by the RSB bus. To avoid circular dependencies, VCC-PL is omitted. On boards with eMMC, VCC-PC is supplied by ELDO1, instead of DCDC1. Signed-off-by:
Stefan Mavrodiev <stefan@olimex.com> [Maxime: Changed the r_pio comment a bit] Signed-off-by:
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Jernej Skrabec authored
Allwinner H6 PWM is similar to that in A20 except that it has additional bus clock and reset line. Note that first PWM channel is connected to output pin and second channel is used internally, as a clock source to AC200 co-packaged chip. This means that any combination of these two channels can be used and thus it doesn't make sense to add pinctrl nodes at this point. Signed-off-by:
Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by:
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Jernej Skrabec authored
H6 PWM block is basically the same as A20 PWM, except that it also has bus clock and reset line which needs to be handled accordingly. Expand Allwinner PWM binding with H6 PWM specifics. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 10 Dec, 2019 11 commits
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Andre Przywara authored
Add the Performance Monitoring Unit (PMU) device tree node to the H3 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. The numbers come from the manual and have been checked in U-Boot and with perf in Linux. Tested with perf record and taskset on an OrangePi Zero. Signed-off-by:
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Andre Przywara authored
Add the Performance Monitoring Unit (PMU) device tree node to the H5 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. As with the A64, the interrupt numbers from the manual were wrong (off by 4), the actual SPI IDs have been gathered in U-Boot, and were verified with perf in Linux. Tested with perf record and taskset on an OrangePi PC2. Signed-off-by:
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Andre Przywara authored
Add the Performance Monitoring Unit (PMU) device tree node to the H6 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. The numbers come from the manual and have been checked in U-Boot and with perf in Linux. Tested with perf record and taskset on a Pine H64. Signed-off-by:
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Jernej Skrabec authored
Beelink X2 box comes with a remote. Add a mapping for it. Signed-off-by:
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Jernej Skrabec authored
Tanix TX6 box comes with a remote. Add a mapping for it. Suggested-by:
Michael Lange <linuxstuff@milaw.biz> Signed-off-by:
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Jernej Skrabec authored
Add new entry for rc-tanix-tx5max in linux,rc-map-name Signed-off-by:
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Corentin Labbe authored
This patch adds the model B of the PineH64. The model B is smaller than the pine64 model A and has no PCIE slot. The only devicetree difference with the pineH64 model A, is the PHY regulator and the HDMI connector node. Signed-off-by:
Corentin Labbe <clabbe@baylibre.com> Signed-off-by:
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Corentin Labbe authored
The current sun50i-h6-pine-h64 DT does not specify which model (A or B) it supports. When this file was created, only modelA was existing, but now both model exists and with the time, this DT drifted to support the model B since it is the most common one. Furtheremore, some part of the model A does not work with it like ethernet and HDMI connector (as confirmed by Jernej on IRC). So it is time to settle the issue, and the easiest way was to state that this DT is for model B. Easiest since only a small name changes is required. Doing the opposite (stating this file is for model A) will add changes (for ethernet and HDMI) and so, will break too many setup. But as asked by the maintainer this patch state this file is for model A. In the process this patch adds the missing compoments to made it work on model A. Signed-off-by:
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Georgii Staroselskii authored
Adds bindings for the new Emlid Neutis N5H3 board. Signed-off-by:
Georgii Staroselskii <georgii.staroselskii@emlid.com> Signed-off-by:
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Georgii Staroselskii authored
Emlid Neutis N5H3 is a version of Emlid Neutis SoM with H3 instead of H5 inside. 6eeb4180 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device") was used as reference. Signed-off-by:
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Georgii Staroselskii authored
A new variant of Emlid Neutis has been inroduced. This one uses H3 instead of H5. The boards are essentially the same. This commit moves non-SoC-specific parts out so that the common parts could be reused with ease. Signed-off-by:
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- 09 Dec, 2019 2 commits
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Clément Péron authored
Enable USB 3.0 phy and host controller. VBUS is directly connected to DCIN 5V and doesn't require to be switched on. Signed-off-by:
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Andre Heider authored
Orange Pi 3 has an on-board IR receiver, enable it. Signed-off-by:
Andre Heider <a.heider@gmail.com> Acked-by:
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