- 10 Oct, 2018 12 commits
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Rex Zhu authored
We need to do some IPs earlier to deal with ordering issues similar to how resume is split into two phases. Will do fw loading via smu/psp between the two phases. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
The variable clean is unnecessary. Reviewed-by:
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Rex Zhu authored
1. one is for create/free bo when init/fini 2. one is for fill the bo before fw loading the ucode bo only need to be created when load driver and free when driver unload. when resume/reset, driver only need to re-fill the bo if the bo is allocated in vram. Suggested by Christian. v2: Return error when bo create failed. Reviewed-by:
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Rex Zhu authored
Fix cg/pg unexpected set in hw init failed case. Reviewed-by:
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Rex Zhu authored
1. only call late_init when hw_init successful, so check status.hw instand of status.valid in late_init. 2. set status.late_initialized true if late_init was not implemented. Reviewed-by:
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Rex Zhu authored
initialize gfx/sdma before dpm features enabled. Acked-by:
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Rex Zhu authored
initialize gfx/sdma before dpm features enabled. Acked-by:
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Emily Deng authored
For the vram_start is 0 case, the gart range will be from 0x0000FFFF00000000 to 0x0000FFFF1FFFFFFF, which will cause the engine hang. So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Tao Zhou authored
Fix CPDMA hang in PRT mode, set CPF_INT_DMA in reg CP_MECx_F32_INT_DIS for Compute and set DISABLE_GFX_HALT_ON_UTCL1_ERROR in reg CP_DEBUG for GFX Affected ASICs: Vega10 Vega12 Raven Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Tested-by:
Yukun.Li <yukun1.li@amd.com> Tested-by:
Maciej.Jesionowski <maciej.jesionowski@amd.com> Acked-by:
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Tao Zhou authored
Add CP_DEBUG register definition. Signed-off-by:
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Hersen Wu authored
RV2 resource is limit to 3 pipes. Limitation should apply to all HW blocks instead of front pipe. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Roman Li authored
[Why] Wrong index for pstate debug test register [How] Add correct index value for dcn1_01 in hubbub1_construct() Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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- 09 Oct, 2018 28 commits
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Rex Zhu authored
initialize gfx/sdma before dpm features enabled. Acked-by:
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Rex Zhu authored
gfx and sdma can be initialized before smu. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Rex Zhu authored
with this interface, gfx/sdma can be initialized before smu. Reviewed-by:
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Rex Zhu authored
ucode bo is needed by request_smu_load_fw, the request_smu_load_fw maybe called by gfx/sdma before smu hw init. so move amdgpu_ucode_bo_init to request_smu_lowd_fw from smu hw init. Reviewed-by:
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Rex Zhu authored
driver don't release the ucode memory when suspend. so don't need to allocate bo when resume back. Reviewed-by:
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Rex Zhu authored
AMDGPU_FW_LOAD_DIRECT is used for bring up. Now it don't work any more. so remove the support. v2: Add warning message if user select AMDGPU_FW_LOAD_DIRECT/AMDGPU_FW_LOAD_PSP on VI. Reviewed-by:
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James Zhu authored
Correct VCN cache window definition. The old one is reused from UVD, and it is not fully correct. Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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James Zhu authored
Replace value with defined macro to make code more readable Signed-off-by:
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James Zhu authored
Use mmUVD_SCRATCH2 tracking decode write point. It will help avoid dpg pause mode hang issue. Signed-off-by:
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James Zhu authored
The following WREG32_SOC15_DPG_MODE will overwrite register mmUVD_CGC_CTRL. This code can be removed. Signed-off-by:
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Nick Alcock authored
So a few days ago I started getting sprays of these warnings -- sorry, but because it was a few days ago I'm not sure what I was running at the time (but it was probably either Stellaris or Chromium). Sep 25 22:06:34 mutilate err: : [ 544.718905] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc Sep 25 22:06:34 mutilate err: : [ 544.718909] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2! Sep 25 22:06:34 mutilate err: : [ 544.719710] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc Sep 25 22:06:34 mutilate err: : [ 544.719714] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2! Sep 25 22:06:34 mutilate err: : [ 544.719862] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc Sep 25 22:06:34 mutilate err: : [ 544.719865] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2! Sep 25 22:06:34 mutilate err: : [ 544.720772] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc Sep 25 22:06:34 mutilate err: : [ 544.720778] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2! Sep 25 22:06:34 mutilate warning: : [ 544.721415] radeon 0000:01:00.0: vbo resource seems too big for the bo followed by a massive stream of "vbo resource seems too big for the bo". The most extreme flood ran from 23:01:58 to 23:02:47 and emitted 91,000 lines of log in that time. This... seems excessive, given that each log message after the first contains more or less no information. So ratelimit these messages. (We probably want to see at least *some* so that the underlying bug can be fixed -- always assuming the bug isn't in unfixable closed-source game code somewhere.) Signed-off-by:
Nick Alcock <nick.alcock@oracle.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Christian König authored
Adding a second irq source because of a different src_id is actually a bug. Signed-off-by:
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Christian König authored
That also simplifies handling quite a bit. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Shirish S authored
[Why] 1. we never submit IBs to the KIQ 2. there seems to be ~500ms delay during amdgpu resume spent in KIQ, hence pointing toward interrupts are not working correctly. [How] remove interrupt handling for KIQ. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>i Signed-off-by:
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Felix Kuehling authored
This mm_struct pointer should never be dereferenced. If running in a user thread, just use current->mm. If running in a kernel worker use get_task_mm to get a safe reference to the mm_struct. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Oded Gabbay <oded.gabbay@gmail.com> Acked-by:
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Pratik Vishwakarma authored
[Why] 1. We never submit IBs to KIQ. 2. Ring test pass without KIQ's ring also. 3. By skipping we see an improvement of around 500ms in the amdgpu's resume time. [How] skip IB tests for KIQ ring type. Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
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Nathan Chancellor authored
Clang generates a warning when it sees a logical not followed by a conditional operator like ==, >, or <. drivers/gpu/drm/scheduler/sched_entity.c:470:6: warning: logical not is only applied to the left hand side of this comparison [-Wlogical-not-parentheses] if (!spsc_queue_count(&entity->job_queue) == 0 || ^ ~~ drivers/gpu/drm/scheduler/sched_entity.c:470:6: note: add parentheses after the '!' to evaluate the comparison first if (!spsc_queue_count(&entity->job_queue) == 0 || ^ ( ) drivers/gpu/drm/scheduler/sched_entity.c:470:6: note: add parentheses around left hand side expression to silence this warning if (!spsc_queue_count(&entity->job_queue) == 0 || ^ ( ) 1 warning generated. It assumes the author might have made a mistake in their logic: if (!a == b) -> if (!(a == b)) Sometimes that is the case; other times, it's just a super convoluted way of saying 'if (a)' when b = 0: if (!1 == 0) -> if (0 == 0) -> if (true) Alternatively: if (!1 == 0) -> if (!!1) -> if (1) Simplify this comparison so that Clang doesn't complain. Fixes: 35e160e7 ("drm/scheduler: change entities rq even earlier") Signed-off-by:Nathan Chancellor <natechancellor@gmail.com> Reviewed-by:
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Rex Zhu authored
The request_smu_load_fw of VI is used to load gfx/sdma ip's firmware. Check whether the gfx/sdma firmware have been loaded successfully in this callback function. if failed, driver can exit to avoid gpu hard hung. if successful, clean the flag reload_fw to avoid duplicated fw load. when suspend/resume, driver need to reload fw. so in suspend, reset the reload_fw flag to true to enable load fw when resume. Reviewed-by:
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Rex Zhu authored
need to know SoftRegsStart value to visit the register UcodeLoadStatus to check fw loading state. Reviewed-by:
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Rex Zhu authored
if upload firmware failed, no matter how many times the function runs again, the same error will be encountered. so remove the duplicated code. Reviewed-by:
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Rex Zhu authored
Move in_suspend flag to adev from gfx, so can be used in other ip blocks, also keep consistent with gpu_in_reset flag. Reviewed-by:
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Rex Zhu authored
On CI/AI, fw was not loaded by smu, but smu's fw still need to be released when driver fini. Reviewed-by:
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Rex Zhu authored
the struct was not in use any more. Reviewed-by:
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Rex Zhu authored
don't need to set fan1_enable to read fan sensors. Reviewed-by:
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Rex Zhu authored
Following lm-sensors 3.0.0, Only enable pwm1 sysfs when fan control mode(pwm1_enable) in manual Reviewed-by:
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Rex Zhu authored
Add fan1_target for get/set fan speed in RPM unit Add fan1_min/fan1_max for get min, max fan speed in RPM unit Add fan1_enable to enable/disable the fan1 sensor v3: drop the hardcode value of min/max rpm in comments pointed out by Alex. v2: query the min/max rpm gpu support instand of hardcode value. Reviewed-by: -
Rex Zhu authored
so user can query the RPM range Reviewed-by:
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Rex Zhu authored
For getting the min/max fan speed in RPM units. Reviewed-by:
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