- 30 Aug, 2019 1 commit
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Andrey Grodzovsky authored
This should be checked at all places job is accessed. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 29 Aug, 2019 38 commits
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Roman Li authored
Enable DC support for renoir. Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Roman Li authored
Hook up the DML changes for renoir. Acked-by:
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Roman Li authored
Need to check for renoir first. Acked-by:
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Bhawanpreet Lakha authored
Add a kconfig option to enable renoir. Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
Enable the building of dcn21 support. Acked-by:
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Bhawanpreet Lakha authored
Add missing parameters, to make dcn21 compile without errors Acked-by:
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Bhawanpreet Lakha authored
Add the rev id for renoir. Acked-by:
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Bhawanpreet Lakha authored
call update_bw_bounding_box in DC construct Acked-by:
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Bhawanpreet Lakha authored
Hook up renoir support to KMS. v2: squash in "Fixes for Renoir in amdgpu_dm" Acked-by:
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Bhawanpreet Lakha authored
add Renoir DCN version in DC and handle it Acked-by:
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Bhawanpreet Lakha authored
rename VM_CONTEXT0 to MMVM_CONTEXT0 as that is the name defined in the register files Acked-by:
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Bhawanpreet Lakha authored
DML provides the display configuration validation as provided by the hw teams. Acked-by:
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Bhawanpreet Lakha authored
Misc display related configuration details. Acked-by:
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Bhawanpreet Lakha authored
Manages the renoir display resources (crtcs, phys, plls, etc.). v2: rebase (Alex) Acked-by:
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Bhawanpreet Lakha authored
Controls display clocks and interfaces with powerplay for clock and power requirements. Acked-by:
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Bhawanpreet Lakha authored
Controls the display hw's interface to memory. v2: rebase (Alex) Acked-by:
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Bhawanpreet Lakha authored
These are the registers used to program the hubbub hw. Acked-by:
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Bhawanpreet Lakha authored
This provides the interface to memory for the display hw. v2: minor cleanup (Alex) Acked-by:
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Bhawanpreet Lakha authored
Provides the interface to configure display interrrupts on renoir. v2: rebase fix (Alex) Acked-by:
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Bhawanpreet Lakha authored
This defines the interface for communicating requirements between DC and powerplay. Acked-by:
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Bhawanpreet Lakha authored
These are the registers used to for the hw sequences for modesetting. Acked-by:
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Bhawanpreet Lakha authored
These are the registers used to program the clock hw. Acked-by:
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Bhawanpreet Lakha authored
add registers for dcn, clk, and renoir ip offsets v2: header cleanup (Alex) v3: Add DPCS registers (Hersen) Acked-by:
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Prike Liang authored
add the get_dpm_ultimate_freq for supporting different swSMU. -v2: Handle the unsupported clock type and read smc message failed case and return error code. Move the smu12 uclk frequency retrieved logic to renoir ppt. -v3: Use goto clause to handle invalidate clk index. Add the limited tag for smu_get_dpm_uclk to avoid other likewise interface introduced. Signed-off-by:Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Prike Liang authored
Should populate DPM clocks tables during hw init,otherwise will suffer from invalidate table. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Prike Liang authored
There is no driver message to enable/disable feature mask for APU. For the sake of APU reusing swSMU interface and assume APU supports all the feature. Signed-off-by:
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Prike Liang authored
Init SDMA HW base configuration and enable idle INT for rn. Signed-off-by:
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Tianci.Yin authored
Fix compute ring test failure in sriov scenario. Reviewed-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
stolen memory should be fixed in visible region. Reviewed-by:
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Colin Ian King authored
There is a spelling mistake in a DRM_DEBUG_DRIVER debug message. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
No need to add new asic cases. This is a sw display implementation, so just drop the error message so when we add new asics, all we have to do is add the virtual dce IP module. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Jean Delvare authored
Comparing adev->family with CHIP constants is not correct. adev->family can only be compared with AMDGPU_FAMILY constants and adev->asic_type is the struct member to compare with CHIP constants. They are separate identification spaces. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Fixes: 62a37553 ("drm/amdgpu: add si implementation v10") Cc: Ken Wang <Qingqing.Wang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Signed-off-by:
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Jean Delvare authored
The driver does not support these sensors yet and there is no point in creating sysfs attributes which will always return an error. Signed-off-by:
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Monk Liu authored
for SOC15/vega10 the BACO reset & mode1 would introduce vram lost in high end address range, current kmd's vram lost checking cannot catch it since it only check very ahead visible frame buffer v2: cover NV as well Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Xiaojie Yuan authored
jpeg pg depends on vcn pg Signed-off-by:
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Xiaojie Yuan authored
Signed-off-by:
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Xiaojie Yuan authored
Signed-off-by:
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Hawking Zhang authored
in_suspend flag should be set in amdgpu_device_suspend/resume in pairs, instead of gfx10 ip suspend/resume function. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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- 27 Aug, 2019 1 commit
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Aaron Liu authored
For picasso(adev->pdev->device == 0x15d8)&raven2(adev->rev_id >= 0x8), firmware is sufficient to support gfxoff. In commit 98f58ada, for picasso&raven2, return directly and cause gfxoff disabled. Fixes: 98f58ada ("drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible") Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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