- 21 Sep, 2020 9 commits
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Thomas Bogendoerfer authored
Remove unused heasder file asm/mach-malta/malta-pm.h. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Remove unused config option ALCHEMY_GPIOINT_AU1000. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Remove unused config option ALCHEMY_GPIOINT_AU1300 and related code. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Move HEART specific parts of mach-ip30/irq.h to asm/sgi/heart.h and IP30 specific parts to sgi-ip30/ip30-common.h. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Huacai Chen authored
Loongson-3 has 16-bytes load/store instructions: gslq and gssq. This patch calculate ra properly when unwinding the stack, if ra is saved by gssq and restored by gslq. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Huacai Chen authored
Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel mode by default. However, gslq/gssq (16-bytes load/store instructions) overrides the instruction format of lwc2/swc2. If we wan't to use gslq/ gssq for optimization in kernel, we should enable COP2 usage in kernel. Please pay attention that in this patch we only enable COP2 in kernel, which means it will lose ST0_CU2 when a process go to user space (try to use COP2 in user space will trigger an exception and then grab COP2, which is similar to FPU). And as a result, we need to modify the context switching code because the new scheduled process doesn't contain ST0_CU2 in its THERAD_STATUS probably. For zboot, we disable gslq/gssq be generated by toolchain. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Huacai Chen authored
Some processors (such as Loongson-3) need to enable CU2 in kernel mode, current set/clear method will lose Status.CU2 during context switching, so use save/restore method instead. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Pujin Shi authored
arch/mips/kernel/branch.c:876:5: error: no previous prototype for '__insn_is_compact_branch' [-Werror=missing-prototypes] Signed-off-by:
Pujin Shi <shipujin.t@gmail.com> Signed-off-by:
Pujin Shi <shipj@lemote.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Jason Yan authored
This addresses the following sparse warning: arch/mips/kernel/setup.c:446:33: warning: symbol 'setup_elfcorehdr_size' was not declared. Should it be static? Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Jason Yan <yanaijie@huawei.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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- 18 Sep, 2020 20 commits
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Paul Cercueil authored
Support for Ingenic chips has been moved to the generic MIPS platform. Update the paths accordingly. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
For each board the MACH_INGENIC_SOC option was selected instead of MACH_INGENIC. Nothing else was changed in the menuconfig. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
Now that all the jz4740 platform code has been removed, and we're left with only a Kconfig and the cpu-feature-overrides.h file, finalize the cleanup process by renaming the jz4740 and include/mach-jz4740 folders to ingenic and include/mach-ingenic. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
Support for Ingenic SoCs is now provided by the arch/mips/generic/ code, so all files in the arch/mips/jz4740/ folder can dropped, except for the Kconfig, and the cpu-feature-overrides.h header file. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
Add support for Ingenic SoCs in arch/mips/generic/. The Kconfig changes are here to ensure that it is possible to compile either a generic kernel that supports Ingenic SoCs, or a Ingenic-only kernel, both using the same code base, to avoid duplicated code. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
128 IRQs is not enough to support Ingenic SoCs. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
There is no reason we can't create compressed kernels here, so select the option SYS_SUPPORTS_ZBOOT. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
The plat_get_fdt() checked that the kernel was booted using UHI before reading the 'fw_passed_dtb' variable. However, this variable is also set when the DT has been appended, or when it has been built into the kernel. Support these usecases by removing the UHI check. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
The function bootcmdline_init() in arch/mips/kernel/setup.c will populate the boot_command_line string using the parameters hardcoded in the kernel, and those provided in the devicetree file. Then, it would append the content of the arcs_cmdline variable, which is filled by the board's plat_mem_setup() function. The plat_mem_setup() function for the generic MIPS board would just copy the current boot_command_line to arcs_cmdline, which is nonsense for two reasons: - the result will be appended to the boot_command_line anyway, so all it does is duplicate every single parameter on the command line; - the code did not perform at all what it's supposed to, which is to retrieve the parameters passed by the bootloader. Fix this by calling fw_init_cmdline() in plat_mem_setup(), which will properly initialize arcs_cmdline to the parameters passed by the bootloader. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
Check for the system_type variable in the get_system_type() function. If non-NULL, return it as the system type. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
The MIPS_GENERIC symbol now won't select any other configuration option. The MIPS_GENERIC_KERNEL will select all the options that the previous MIPS_GENERIC option did select, and will select MIPS_GENERIC as well. The whole point of this, is that it now becomes possible to compile a kernel for a SoC supported by the arch/mips/generic/ code, without making that kernel generic itself. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
The previous code was doing: BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); This only worked as the "cpu_has_counter" macro was overridden in <cpu-feature-overrides.h>. The default "cpu_has_counter" macro is non-constant, which triggered the BUG_ON() independently of the value returned by the macro. What we want to check here, is that *if* the macro was overridden to a compile-time constant, then must be defined to zero, otherwise it's a bug. So the correct check is: BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter); Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
XBurst CPUs present in Ingenic SoCs have virtually tagged caches, according to the <cpu-features-override.h> header. Add that information to cpu_probe_ingenic(). Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
Previously, in cpu_probe_ingenic(), c->writecombine was set to _CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when CONFIG_MACH_INGENIC was set. This made it impossible to support multiple CPUs. Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA directly and removing the dependency on CONFIG_MACH_INGENIC. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Paul Cercueil authored
Since INGENIC_GENERIC_BOARD was introduced, the JZ4740_QI_LB60 option is no longer the default, so the symbol has to be selected by the defconfig, otherwise the kernel built will be for a generic Ingenic board and won't have the Device Tree blob built-in. Cc: stable@vger.kernel.org # v5.7 Fixes: 62249209 ("MIPS: ingenic: Default to a generic board") Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Huacai Chen authored
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256). Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Youling Tang authored
Remove some unused code. Signed-off-by:
Youling Tang <tangyouling@loongson.cn> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Qinglang Miao authored
Note that error handling on the result of a call to platform_get_resource() is unneeded when the value is passed to devm_ioremap_resource(), so remove it. Then use the helper function that wraps the calls to platform_get_resource() and devm_ioremap_resource() together. Signed-off-by:
Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Zhang Qilong authored
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by:
Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Wei Li authored
Rename the header guard of r4k-timer.h from __ASM_R4K_TYPES_H to __ASM_R4K_TIMER_H what corresponding with the file name. Signed-off-by:
Wei Li <liwei391@huawei.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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- 07 Sep, 2020 11 commits
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Thomas Bogendoerfer authored
After conversion of all WAR defines we can now remove all mach-*/war.h files. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX. By using the version check we can remove the define. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS. So using this option directly lets and remove define. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
SB1250 uart bug is related to PASS 2 workarounds. Use config CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Use a new config option to enable MIPS 34K ITLB workaround and remove define from different war.h files. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Use a new config option to enabel R1000_LLSC workaound and remove define from different war.h files. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Use a new config option to enable I-cache refill workaround and remove define from different war.h files. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Use a new config option to enable TX49XX I-cache index invalidate workaround and remove define from different war.h files. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented, so removing defines for it won't change anything. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Use a new config option to enable R4600 V2 cacheop hit workaround and remove define from different war.h files. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer authored
Use a new config option to enable R4600 V1 cacheop hit workaround and remove define from the different war.h files. Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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