ppc64 tlb flush rework from Paul Mackerras

Instead of doing a double pass of the pagetables, we batch things
up in the pte flush routines and then shoot the batch down in
flush_tlb_pending.

Our page aging was broken, we never flushed entries out of the ppc64
hashtable. We now flush in ptep_test_and_clear_young.

A number of other things were fixed up in the process:

- change ppc64_tlb_batch to per cpu data
- remove some LPAR debug code
- be more careful with ioremap_mm inits
- clean up arch/ppc64/mm/init.c, create tlb.c

From: Anton Blanchard <anton@samba.org>

Binutils uses the recent mtcrf optimisation when compiling for a POWER4
target.  Unfortunately this causes a program check on POWER3.  We required
compiling for POWER4 so the tlbiel instruction would be recognised.

For the moment we hardwire the tlbiel instruction, longer term we can use the
binutils -many flag.

From: Anton Blanchard <anton@samba.org>

Attached is a patch which replaces all the uses of the old device tree API in
arch/ppc64.  Patch is against 2.6.0-test5 (cset 1.1328) from ameslab bk, plus
the patch from my previous message.  I've tested this on a pSeries LPAR.

add power4 flag for assembler, needed for tlbiel.

ppc64: remove local_flush_* functions, just define them directly

get rid of global lock on hpte insert and remove, use a software bit
 for pSeries and the relevant interfaces for pSeries LPAR to avoid
 races.
preload hpte entries in update_mmu_cache.
keep cpu_vm_mask and use tlbiel when mm has only run locally
batch tlb flushes where possible.
add large page support in preparation for generic large page support.
Remove HPTENOIX, we always put slot information into linux ptes now.
Note: pSeries and pSeries LPAR so far, iSeries coming next.