- 15 May, 2018 40 commits
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Huang Rui authored
Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Huang Rui authored
drm/amdgpu: revise init_rlc_save_restore_list behavior to support latest register_list_format/register_restore table RLC save/restore list will be used on CGPG and GFXOFF function, it loads two bin table of register_list_format/register_restore in RLC firmware. Signed-off-by:
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Huang Rui authored
Remove gfx_v9_0_enable_sck_slow_down_on_power_up/down and CP power gating enabling functions because they only need to be called on setting power gating behavior. We keep it in set_powergating callback to enable/disable PG in late_init. Signed-off-by:
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Huang Rui authored
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Huang Rui authored
RLC save/restore list cntl/gpm_mem/srm_mem ucodes are used for CGPG and gfxoff function. Signed-off-by:
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Huang Rui authored
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Huang Rui authored
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Kenneth Feng authored
For the dummy ACG fuses,need to disable ACG, otherwise corruption will be caused. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Christian König authored
Just note if a BO was imported/exported. Signed-off-by:
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Kenneth Feng authored
update vega12 smu interface. Signed-off-by:
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Junwei Zhang authored
v2: fix compiling warning Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Flora Cui authored
fix settings. Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
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Rex Zhu authored
It is caused by 'commit d6c9a7dc86cd ("drm/amd/pp: Move common code to smu_helper.c")' Reviewed-by:Evan Quan <evan.quan@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Chunming Zhou authored
Otherwise, cpu stuck for 22s with kernel panic. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Marek Olšák authored
There is a new IB flag that enables this new behavior. Full invalidation is unnecessary for RELEASE_MEM and doesn't make sense when draw calls from two adjacent gfx IBs run in parallel. This will be the new default for Mesa. v2: bump the version Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Chunming Zhou authored
if domain is illegal, we should return error. v2: remove duplicated domain checking. Signed-off-by:
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Chunming Zhou authored
When GEM needs to fallback to GTT for VRAM BOs we still want the preferred domain to be untouched so that the BO has a cance to move back to VRAM in the future. Signed-off-by:
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Christian König authored
Turned out that this locks up some bare metal Vega10. v2: fix stupid typo Signed-off-by:
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Pixel Ding authored
Make sure main thread won't update last_sched fence when entity is cleanup. Fix a racing issue which is caused by putting last_sched fence twice. Running vulkaninfo in tight loop can produce this issue as seeing wild fence pointer. v2: squash in build fix (Christian) Signed-off-by:
Pixel Ding <Pixel.Ding@amd.com> Reviewed-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
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Pixel Ding authored
Fix the potential memleak since scheduler main thread always hold one last_sched fence. Signed-off-by:
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Alex Deucher authored
Useful for info gathering about what firmwares are in use in the driver. Reviewed-by:
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Rex Zhu authored
Make sure to update the MCLK and SCLK flags when setting the VDDC flags due to dependencies. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
v2: check reserved vram size before allocate. Reviewed-by:
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Chunming Zhou authored
After that, we can easily add new parameter when need. v2: a) rebase. b) Initialize struct amdgpu_bo_param, future new member could only be used in some one case, but all member should have its own initial value. Signed-off-by:
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Chunming Zhou authored
amdgpu_bo_create has too many parameters, and used in too many places. Collect them to one structure. Signed-off-by:
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Yongqiang Sun authored
Linux doesn't know lid state, better to check dig enable value from register. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Yongqiang Sun authored
Use lid state only to determine fast boot optimization is not enough. For S3/Resume, due to bios isn't involved in boot, eDP wasn't light up, while lid state is open, if do fast boot optimization, eDP panel will skip enable link and result in black screen after boot. And becasue of bios isn't involved, no matter UEFI or Legacy boot, BIOS_SCRATCH_3 value should be 0, use this to determine the case. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Eric Bernstein authored
Added dchububu.h header file for common enum/struct definitions. Added new interface functions get_dcc_compression_cap, dcc_support_swizzle, dcc_support_pixel_format. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Yongqiang Sun authored
For legacy enable boot up with lid closed, eDP information couldn't be read correctly via SBIOS_SCRATCH_3 results in eDP cannot be light up properly when open lid. Check lid state instead can resolve the issue. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Leo (Sunpeng) Li authored
Hardware understands the regamma LUT as a piecewise linear function, with points spaced exponentially along the range. We previously programmed the LUT for range [2^-10, 2^0). This causes (normalized) color values of 1 (=2^0) to miss the programmed LUT, and fall onto the end region. For DCE, the end region is extrapolated using a single (base, slope) pair, using the max y-value from the last point in the curve as base. This presents a problem, since this value affects all three color channels. Scaling down the intensity of say - the blue regamma curve - will not affect it's end region. This is especially noticiable when using RedShift. It scales down the blue and green channels, but leaves full-intensity colors unshifted. Therefore, extend the range to cover [2^-10, 2^1) by programming another hardware segment, containing only one point. That way, we won't be hitting the end region. Note that things are a bit different for DCN, since the end region can be set per-channel. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Eric Bernstein authored
Signed-off-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Roman Li authored
Adding missing call to cache current backlight values. Otherwise the brightness resets to default value on resume. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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