- 21 Jul, 2011 10 commits
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Kamil Debski authored
Add support for MFC device to plat-s5p, mach-exynos4, mach-s5pv210: - clock support - memory mapping and reserving - s5p_device_mfc platform device Signed-off-by:
Kamil Debski <k.debski@samsung.com> Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Jingoo Han authored
This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel on Samsung SMDKC210 board. Signed-off-by:
Jingoo Han <jg1.han@samsung.com> Signed-off-by:
Jonghun Han <jonghun.han@samsung.com> Signed-off-by:
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Jonghun Han authored
This patch adds platform device s5p_device_fimd0 for EXYNOS4 FIMD0. EXYNOS4 has two FIMDs(FIMD0, FIMD1). FIMD1 will be added later. Some definitions used to enable EXYNOS4 FIMD0 are added. Signed-off-by:
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Jonghun Han authored
This patch adds resource definitions for EXYNOS4 FIMD. IRQ and SFR definitions are added. Signed-off-by:
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Jingoo Han authored
According to SoC name, EXYNOS4, this patch changes devname for FIMD from 's5pv310-fb' to 'exynos4-fb'. Signed-off-by:
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Kukjin Kim authored
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Sangbeom Kim authored
To handle i2s0 interrupt and To fix compilation error adds IRQ_I2S0 for exynos4, s3c64xx, s5p64x0 Signed-off-by:
Sangbeom Kim <sbkim73@samsung.com> [kgene.kim@samsung.com: Fixed build failure due to inclusion] Signed-off-by:
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Sangbeom Kim authored
Exynos4 and S5PC110(S5PV210) has Internal dma(idma) in AUDSS. To support idma, register idma platform device. and Exynos4 and S5PC110 has different IDMA address. TO handle different IDMA address, register idma platform data Signed-off-by:
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MyungJoo Ham authored
We need more registers to be saved and restored for PM of EXYNOS4210. Otherwise, with additional drivers running, suspend-to-RAM fails to wake up properly. This patch adds registers omitted in the initial PM patches. Signed-off-by:
MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by:
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MyungJoo Ham authored
These registers are crucial for PM to work properly. Signed-off-by:
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- 20 Jul, 2011 30 commits
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Thomas Abraham authored
This is temporary patch for building with clkdev. Signed-off-by:
Thomas Abraham <thomas.ab@samsung.com> Signed-off-by:
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Thomas Abraham authored
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Seungwon Jeon authored
This patch adds platform device for Synopsys DesignWare Multimedia Card Interface driver. Signed-off-by:
Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by:
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MyungJoo Ham authored
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MyungJoo Ham authored
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MyungJoo Ham authored
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MyungJoo Ham authored
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MyungJoo Ham authored
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MyungJoo Ham authored
MAX8997/17042, which are used by Exynos4-NURI, use additional IRQ numbers after GPIO's IRQs. The patch creates some room for those devices. Signed-off-by:
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MyungJoo Ham authored
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MyungJoo Ham authored
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MyungJoo Ham authored
- Fixed: 12bit precision is lost at suspend/resume - Updated: use pm_dev_ops Signed-off-by:
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MyungJoo Ham authored
In S5PV210/S5PC110/EXYNOS4, ADCMUX channel selection uses ADCMUX register, not ADCCON register. This patch corrects the behavior of SAMSUNG-ADC for such CPUs. Signed-off-by:
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MyungJoo Ham authored
This patch allows the Samsung ADC driver to enable VDD regulator at probe and resume and to disable at exit and suspend. In a platform where ADC's VDD regulator is not "always-on", this control is required although this patch does not provide fine-grained power control (turning on the regulator only when being accessed). However, if VDD regulator ("vdd" for the adc device) is not provided, the regulator control will not be activated because there are platforms that do not provide regulator for ADC device. arch_initcall has been modified to module_init in order to allow regulators to be available at probe. Signed-off-by: -
Jaecheol Lee authored
The PLL restore routine supports waiting pll locking. If PLL is enabled in restoring sequence, it should wait until PLL is locked. Signed-off-by:
Jaecheol Lee <jc.lee@samsung.com> Signed-off-by:
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Jaecheol Lee authored
This patch adds save/restore values for Power Control Register and Diagnostic Register for PM. Signed-off-by:
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Jaecheol Lee authored
We need to balance between set and check S5P_CENTRAL_SEQ_CONFIGURATION register in syscore_ops suspend/resume function when failure in enter suspend mode. Moved this register setting for PM for the purpose of balancing. Signed-off-by:
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Jaecheol Lee authored
Since early wakeup can be handled in pm so we don't need masking interrupts of external GIC. When the early wakeup interrupt happens, PMU(Power Management Unit) ignores WFI instruction. This means that PC(Program Counter) passed without any changes. This patch can handle that case by early wakeup interrupt. Signed-off-by:
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Jaecheol Lee authored
PMU(Power Management Unit) configuraion for S2RAM(SLEEP) is removed and using function which provided by PMU support code to configure PMU register. Signed-off-by:
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Jaecheol Lee authored
EXYNOS4 supports 3 different system level power down mode by PMU (Power Management Unit). Each power down mode need to configure many PMU registers with different value. This patch supports function to configure PMU registers with pre-defined values in PMU code. This function may be used by PM code and AFTR/LPA support driver. Signed-off-by:
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Naveen Krishna Chatradhi authored
This patch adds spdif to the machine supported device list for SMDKV310. Signed-off-by:
Naveen Krishna Chatradhi <ch.naveen@samsung.com> Acked-by:
Jassi Brar <jassisinghbrar@gmail.com> Signed-off-by:
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JungHi Min authored
To insert the code for power on/off with pmu control to support hotplug in/out core1 As for hotplug.c, the codes for core1 to be hotplug in/out is inserted. As for regs-pmu.h, S5P_CORE_LOCAL_PWR_EN is defined. As for platsmp.c, the codes for core1 to be powered on is inserted. Signed-off-by:
JungHi Min <junghi.min@samsung.com> Signed-off-by:
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Changhwan Youn authored
This patch adds chained IRQ enter/exit functions to uart interrupt handler in order to function correctly on primary controllers with different methods of flow control. Signed-off-by:
Changhwan Youn <chaos.youn@samsung.com> Signed-off-by:
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Changhwan Youn authored
External GIC cannot support PPI (Private Peripheral Interrupt) for ARM private timers. Thus MCT should be selected as clock event timers by default. Signed-off-by:
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Changhwan Youn authored
For full support of power modes, this patch adds implementation external GIC on EXYNOS4. External GIC of Exynos4 cannot support register banking so several interrupt related code for CPU1 should be different from that of CPU0. Signed-off-by:
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Changhwan Youn authored
Since Samsung EXYNOS4210 cannot support register banking in GIC, so needs to update CPU interface base address. The 'gic_chip_data' is used for it, this patch moves gic_chip_data structure declaraton to arch/arm/include/asm/hardware/gic.h to use it. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
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Changhwan Youn authored
IRQ_MCT_L1 is connected directly to GIC in external GIC mapping, while in internal GIC mapping, it is connected to GIC through interrupt combiner. Therfore the affinity for mct1 event timer interrupt should be changed through IRQ_MCT_L1. Signed-off-by:
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Changhwan Youn authored
To support external GIC needs to update mapping of interrupt number. This patch modifies it for external GIC and accordingly removes the unused code. Signed-off-by:
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Changhwan Youn authored
This patch adds external GIC io memory mapping to support external GIC on EXYNOS4. Signed-off-by:
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Inderpal Singh authored
Adds device definition to enable SATA on SMDKV310 Signed-off-by:
Inderpal Singh <inderpal.s@samsung.com> Signed-off-by:
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