- 10 Sep, 2009 40 commits
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Michael S. Tsirkin authored
switch pit creation to slots_lock. slots_lock is already taken for read everywhere, so we only need to take it for write when creating pit. This is in preparation to removing in_range and kvm->lock around it. Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
Avi Kivity <avi@redhat.com>
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Michael S. Tsirkin authored
switch coalesced mmio slots_lock. slots_lock is already taken for read everywhere, so we only need to take it for write when changing zones. This is in preparation to removing in_range and kvm->lock around it. [avi: fix build] Signed-off-by:
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Michael S. Tsirkin authored
slots_lock is taken everywhere when device ops are called. Document this as we will use this to rework locking for io. Signed-off-by:
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Marcelo Tosatti authored
Change kvm_vcpu_is_bsp to use vcpu_id instead of bsp_vcpu pointer, which is only initialized at the end of kvm_vm_ioctl_create_vcpu. Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
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Marcelo Tosatti authored
Return EOPNOTSUPP for KVM_TRACE_ENABLE/PAUSE/DISABLE ioctls. Signed-off-by:
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Marcelo Tosatti authored
[avi: make it build] [avi: fold trace-arch.h into trace.h] CC: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by:
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Andre Przywara authored
KVM will inject a #GP into the guest if that tries to access unhandled MSRs. This will crash many guests. Although it would be the correct way to actually handle these MSRs, we introduce a runtime switchable module param called "ignore_msrs" (defaults to 0). If this is Y, unknown MSR reads will return 0, while MSR writes are simply dropped. In both cases we print a message to dmesg to inform the user about that. You can change the behaviour at any time by saying: # echo 1 > /sys/modules/kvm/parameters/ignore_msrs Signed-off-by:
Andre Przywara <andre.przywara@amd.com> Signed-off-by:
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Andre Przywara authored
If the Linux kernel detects an C1E capable AMD processor (K8 RevF and higher), it will access a certain MSR on every attempt to go to halt. Explicitly handle this read and return 0 to let KVM run a Linux guest with the native AMD host CPU propagated to the guest. Signed-off-by:
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Andre Przywara authored
Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM does not handle the needed MSR, the injected #GP will panic the Linux kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux boot with an AMD K8 family guest CPU. Signed-off-by:
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Marcelo Tosatti authored
Correct missing locking in a few places in x86's vm_ioctl handling path. Signed-off-by:
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Joerg Roedel authored
[avi: fix build on non-x86] Signed-off-by:
Joerg Roedel <joerg.roedel@amd.com> Signed-off-by:
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Joerg Roedel authored
This function is required by KVM. Signed-off-by:
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Christian Borntraeger authored
Since commit 854b5338196b1175706e99d63be43a4f8d8ab607 Author: Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> KVM: s390: streamline memslot handling s390 uses the values of the memslot instead of doing everything in the arch ioctl handler of the KVM_SET_USER_MEMORY_REGION. Unfortunately we missed to set the userspace_addr of our memslot due to our s390 ifdef in __kvm_set_memory_region. Old s390 userspace launchers did not notice, since they started the guest at userspace address 0. Because of CONFIG_DEFAULT_MMAP_MIN_ADDR we now put the guest at 1M userspace, which does not work. This patch makes sure that new.userspace_addr is set on s390. This fix should go in quickly. Nevertheless, looking at the code we should clean up that ifdef in the long term. Any kernel janitors? Signed-off-by:Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by:
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Andre Przywara authored
Handle #UD intercept of the sysexit instruction in 64bit mode returning to 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by:
Christoph Egger <christoph.egger@amd.com> Signed-off-by:
Amit Shah <amit.shah@redhat.com> Signed-off-by:
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Andre Przywara authored
Handle #UD intercept of the sysenter instruction in 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by:
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Andre Przywara authored
Handle #UD intercept of the syscall instruction in 32bit compat mode on an Intel host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Save the RIP and EFLAGS to the correct registers. [avi: fix build on i386 due to missing R11] Signed-off-by:
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Andre Przywara authored
Add the flags needed for syscall, sysenter and sysexit to the opcode table. Catch (but for now ignore) the opcodes in the emulation switch/case. Signed-off-by:
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Andre Przywara authored
Signed-off-by:
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Andre Przywara authored
Add the opcodes for syscall, sysenter and sysexit to the list of instructions handled by the undefined opcode handler. Signed-off-by:
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Marcelo Tosatti authored
This allows use of the powerful ftrace infrastructure. See Documentation/trace/ for usage information. [avi, stephen: various build fixes] [sheng: fix control register breakage] Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Sheng Yang <sheng@linux.intel.com> Signed-off-by:
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Alexander Graf authored
While trying to get Hyper-V running, I realized that the interrupt injection mechanisms that are in place right now are not 100% correct. This patch makes nested SVM's interrupt injection behave more like on a real machine. Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Alexander Graf authored
SVM adds another way to do INVLPG by ASID which Hyper-V makes use of, so let's implement it! For now we just do the same thing invlpg does, as asid switching means we flush the mmu anyways. That might change one day though. Signed-off-by:
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Alexander Graf authored
Hyper-V uses some MSRs, some of which are actually reserved for BIOS usage. But let's be nice today and have it its way, because otherwise it fails terribly. [jaswinder: fix build for linux-next changes] Signed-off-by:
Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by:
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Alexander Graf authored
Hyper-V accesses MSR_IGNNE while running under KVM. Signed-off-by:
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Avi Kivity authored
The host never reads cr2 in process context, so are free to clobber it. The vmx code does this, so we can safely remove the save/restore code. Signed-off-by: -
Avi Kivity authored
cr2 changes only rarely, and writing it is expensive. Avoid the costly cr2 writes by checking if it does not already hold the desired value. Shaves 70 cycles off the vmexit latency. Signed-off-by: -
Jan Kiszka authored
The current code tries to optimize the setting of KVM_REQ_PENDING_TIMER but used atomic_inc_and_test - which always returns true unless pending had the invalid value of -1 on entry. This patch drops the test part preserving the original semantic but expressing it less confusingly. Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by:
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Jan Kiszka authored
Minor issue that likely had no practical relevance: the kvm timer function so far incremented the pending counter and then may reset it again to 1 in case reinjection was disabled. This opened a small racy window with the corresponding VCPU loop that may have happened to run on another (real) CPU and already consumed the value. Fix it by skipping the incrementation in case pending is already > 0. This opens a different race windows, but may only rarely cause lost events in case we do not care about them anyway (!reinject). Signed-off-by:
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Gleb Natapov authored
Most of the time IRR is empty, so instead of scanning the whole IRR on each VM entry keep a variable that tells us if IRR is not empty. IRR will have to be scanned twice on each IRQ delivery, but this is much more rare than VM entry. Signed-off-by:
Gleb Natapov <gleb@redhat.com> Signed-off-by:
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Gleb Natapov authored
Replace previous exception with a new one in a hope that instruction re-execution will regenerate lost exception. Signed-off-by:
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Marcelo Tosatti authored
Disable usage of 2M pages if VMX_EPT_2MB_PAGE_BIT (bit 16) is clear in MSR_IA32_VMX_EPT_VPID_CAP and EPT is enabled. [avi: s/largepages_disabled/largepages_enabled/ to avoid negative logic] Signed-off-by:
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Marcelo Tosatti authored
Handler for EPT misconfiguration which checks for valid state in the shadow pagetables, printing the spte on each level. The separate WARN_ONs are useful for kerneloops.org. Signed-off-by:
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Marcelo Tosatti authored
Required by EPT misconfiguration handler. Signed-off-by:
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Marcelo Tosatti authored
This way there is no need to add explicit checks in every for_each_shadow_entry user. Signed-off-by:
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Marcelo Tosatti authored
Required for EPT misconfiguration handler. Signed-off-by:
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Andre Przywara authored
The performance counter MSRs are different for AMD and Intel CPUs and they are chosen mainly by the CPUID vendor string. This patch catches writes to all addresses (regardless of VMX/SVM path) and handles them in the generic MSR handler routine. Writing a 0 into the event select register is something we perfectly emulate ;-), so don't print out a warning to dmesg in this case. This fixes booting a 64bit Windows guest with an AMD CPUID on an Intel host. Signed-off-by:
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Marcelo Tosatti authored
Make the audit code aware of largepages. Signed-off-by:
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Marcelo Tosatti authored
- Fail early in case gfn_to_pfn returns is_error_pfn. - For the pre pte write case, avoid spurious "gva is valid but spte is notrap" messages (the emulation code does the guest write first, so this particular case is OK). Signed-off-by:
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Marcelo Tosatti authored
It is valid to set non leaf sptes as notrap. Signed-off-by:
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Marcelo Tosatti authored
- Unsync pages contain writable sptes in the rmap. - rmaps do not exclusively contain writable sptes anymore. Signed-off-by:
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