- 13 Oct, 2008 32 commits
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Anton Vorontsov authored
The fsl_upm nand driver fails to build because fsl_lbc_lock isn't exported, the lock is needed by the inlined fsl_upm_run_pattern() function: ERROR: "fsl_lbc_lock" [drivers/mtd/nand/fsl_upm.ko] undefined! Dave Jones purposed to export the lock, but it is better to just uninline the fsl_upm_run_pattern(). When uninlined we also no longer need the exported fsl_lbc_regs, and both fsl_lbc_lock and fsl_lbc_regs could be marked static. While at it, also add some missing includes that we should have included explicitly. Reported-by:
Dave Jones <davej@redhat.com> Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Anton Vorontsov authored
The StMicro NAND chip (512Mbit, 64MB) is connected to the local bus, the first local bus' user-programmable machine is configured by the firmware to work with NAND chips. QE GPIO pin is used to poll the NAND's Ready-Not-Busy signal. Signed-off-by:
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Martyn Welch authored
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). This patch adds support for the registers held in the devices main FPGA, exposing extra information about the revision of the board through cpuinfo. Signed-off-by:
Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by:
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Anton Vorontsov authored
On MPC8349E-mITX, MPC8315E-RDB and MPC837x-RDB boards there is a Freescale MC9S08QG8 (MCU) chip with the custom firmware pre-programmed. The chip is used to power-off the board by the software, and to control some GPIO pins. Signed-off-by:
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Timur Tabi authored
The Freescale Elo DMA driver binds to all DMA channels in the device tree that are compatible with "fsl,eloplus-dma-channel". This conflicts with the sound drivers for the MPC8610 HPCD. On this board, the SSI uses two DMA channels and therefore those channels are not available for general purpose use. We change the compatible properties for these channels "fsl,ssi-dma-channel". This works because the sound drivers don't actually check the compatible property when it grabs channels. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
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Timur Tabi authored
The "fsl,ssi-dma-channel" compatible property is used to specify a DMA channel on the Freescale Elo DMA controller that should be used exclusively by the Freescale SSI audio controller. When a property is marked as such, the Elo DMA driver will ignore it, and so it will be available for the sound drivers. Signed-off-by:
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Timur Tabi authored
Because CHRP and PMAC are by default enabled, several non-CHRP and non-PMAC PowerPC defconfigs will have these Kconfig options set erroneously. Signed-off-by:
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Anton Vorontsov authored
of/base.c matches on the first (most specific) entries, which isn't quite practical but it was discussed[1] that this won't change. The bindings specifies verbose information for the devices, but it doesn't fit in the I2C ID's 20 characters limit. The limit won't change[2], and the bindings won't change either as they're correct. So we have to put an exception for the MPC8349E-mITX-compatible MCUs. Signed-off-by:
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Anton Vorontsov authored
The RTC is sitting on the I2C1 bus at address 0x68. RTC interrupt signal is connected to the IPIC's EXT3 interrupt line. Signed-off-by:
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Timur Tabi authored
Early versions of the Freescale DIU framebuffer driver depended on a bootmem allocation of memory for the video buffer. The need for this feature was removed in commit 6b51d51a, so now we can remove the platform-specific code that allocated that memory. Signed-off-by:
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Milton Miller authored
b38fd42f added false dependencys to order the load of upper and lower halfs of the pte, but only adjusted whitespace instead of deleting the old load in the iside handler, letting the hardware see the non-dependent load. This patch removes the extra load. Signed-off-by:
Milton Miller <miltonm@bga.com> Signed-off-by:
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John Rigby authored
Uses mpc83xx_add_bridge in fsl_pci.c Adds second register tuple to pci node register property as done for 83xx device trees in a previous patch. Signed-off-by:
John Rigby <jrigby@freescale.com> Acked-by:
Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
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John Rigby authored
Modify mpc83xx_add_bridge to get config space register base address from the device tree instead of immr + hardcoded offset. 83xx pci nodes have this change: register properties now contain two address length tuples: First is the pci bridge register base, this has always been there. Second is the config base, this is new. This is documented in dts-bindings/fsl/83xx-512x-pci.txt The changes accomplish these things: mpc83xx_add_bridge no longer needs to call get_immrbase it uses hard coded addresses if the second register value is missing Signed-off-by: -
John Rigby authored
The class of the MPC5121 pci host bridge is PCI_CLASS_BRIDGE_OTHER while other freescale host bridges have class set to PCI_CLASS_PROCESSOR_POWERPC. This patch makes fixup_hide_host_resource_fsl match PCI_CLASS_BRIDGE_OTHER in addition to PCI_CLASS_PROCESSOR_POWERPC. Signed-off-by:
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Anton Vorontsov authored
In the standalone setup the board's CPLD disables the PCI internal arbiter, thus any access to the PCI bus will hang the board. The common way to disable particular devices in the device tree is to put the "status" property with any value other than "ok" or "okay" into the device node we want to disable. So, when there is no PCI arbiter on the bus the u-boot adds status = "broken (no arbiter)" property into the PCI controller's node, and so marks the PCI controller as unavailable. Signed-off-by:
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Anton Vorontsov authored
Specifying user-selectable option in the qe_lib/Kconfig was a bad idea because the qe_lib/Kconfig is included into the top level Kconfig, and thus the QE_GPIO option appears at the top level menu. This patch effectively moves the QE_GPIO option under the platform menu instead. Signed-off-by:
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Timur Tabi authored
Modify the Kconfig so that Freescale QUICC Engine (QE) support is a selectable option, thereby allowing users to compile kernels without any QE support. The drawback is that QE support is now disabled by default on platforms that have a QE, and so a defconfig is needed to enable QE and QE devices (like UCC GETH). Fortunately, all the current relevant defconfigs do that already. Signed-off-by:
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Martyn Welch authored
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). A number of MPC8641D based route interrupts for on-board interrupts through a FPGA based interrupt controller, which is chained with the MPC8641D's mpic. This patch provides a basic driver to allow basic routing of interrupts to the mpic. Signed-off-by:
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Kumar Gala authored
Add interrupt info to the MPC8536DS .dts for the RTC Signed-off-by: -
Milton Miller authored
The comment in the code was asking "Do we have to do this?", and according to x86 and s390 the answer is no, the scheduler will do it before calling the arch hook. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Milton Miller authored
A single full sync (mb()) is requrired to order the mmio to the qirr reg with the set or clear of the message word. However, test_and_clear_bit has the effect of smp_mb() and we are not doing any other io from here, so we don't need a mb per bit processed. Signed-off-by:
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Milton Miller authored
Several printks were broken at word boundaries for line length. Some even referred to old function names. Using __func__ and changing the text slightly for the format allows these printk formats to fit on one line. Signed-off-by:
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Milton Miller authored
It is physically per-cpu, and we want the irq layer to treat it that way. Signed-off-by:
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Milton Miller authored
EOI normally has the side effect of returning the cpu to the base priority to recieve the next interrupt. This is actually controlled by the top byte of the xirr register. When we are exiting the kernel in kexec we must eoi the ipi for the next kernel because we never return from the handler, but we want to leave interrupt delivery blocked until the next kernel takes action. Since the hardware ipi vector is fixed, its easiest to just do the eoi explicitly. Signed-off-by:
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Milton Miller authored
This factors out processors joining and unjoining the Global Interrupt Queue into a separate function. There is a bit of math to calculate the arguments to rtas to join or leave the global interrupt queue, and a warning on failure afterwards. Make a helper for the 3 callers. Signed-off-by:
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Milton Miller authored
We only need to check the ibm,interrupt-server#-size property once, not once per global server and thread. We can use !CONFIG_SMP cpu masks and hard_smp_processor_id() to avoid an ifdef. Put the node when breaking out of the loop on lpar systems. Signed-off-by:
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Milton Miller authored
Trim unneeded includes from xics.c. We don't use signals or gfp flags, we use only OF functions and don't need prom, and the 8259 is now handled by our caller. Signed-off-by:
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Milton Miller authored
The xirr is 32 bits in hardware, but the hypervisor requries the upper bits of the register to be clear on the hcall. By changing the type from signed to unsigned int we can drop masking it back to 32 bits. Signed-off-by:
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Milton Miller authored
Now that xics_update_irq_servers is called only from init and hotplug code, it becomes possible to clean up the ordering of functions in the file, grouping them but the interfaces they implement. Signed-off-by:
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Milton Miller authored
xics supports only one ipi per cpu, and expects software to use some queue to know why the interrupt was sent. In Linux, we use a an array of bitmaps indexed by cpu to identify the message. Currently the bits are set in smp.c and decoded in xics.c, with the data structure in a header file. Consolidate the code in xics.c similar to mpic and other interrupt controllers. Also, while making the the array static, the message word doesn't need to be volatile as set_bit and test_clear_bit take care of it for us, and put it under ifdef smp. Signed-off-by:
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- 12 Oct, 2008 5 commits
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Kumar Gala authored
Previously the FDT header field boot_cpuid_phys wasn't actually used on ppc32. Instead the physical boot cpuid was assumed to be 0 for !CONFIG_SMP. Signed-off-by:
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Josh Boyer authored
There is an old workaround in the sysdev/Makefile for dealing with arch/ppc vs. arch/powerpc compiles. This is no longer needed as arch/ppc is dead. Signed-off-by:
Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by:
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Anton Vorontsov authored
The helper is factored out of of_get_gpio(). Will be used by the QE pin multiplexing functions (they need to parse the gpios = <> too). Signed-off-by:
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Milton Miller authored
Currently, every time we determine which irq server to use, we check if default_server, which is the id of the bootcpu, is still online. But default_server is a hardware cpu, not the logical cpu id needed to index cpu_online_map. Since the default server can only go offline during a cpu hotplug event, explicitly check the default server and choose the new one when we move irqs away from the cpu being offlined. This has the added benefit of only needing the boot_cpuid to be updated and not relying on the cpu being marked offline during migrate_irqs_away. Also, since xics_update_irq_servers only reads device tree information, we can call it before xics_init_host in xics_init_IRQ and then default_server will always be valid when we can reach get_irq_server via the host ops. Signed-off-by:
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Milton Miller authored
When reciving an irq vector that does not have a linux mapping, the kernel prints a message and calls RTAS to disable the irq source. Previously the kernel did not EOI the interrupt, causing the source to think it is still being processed by software. While this does add an additional layer of protection against interrupt storms had RTAS failed to disable the source, it also prevents the interrupt from working when a driver later enables it. (We could alternatively send an EOI on startup, but that strategy would likely fail on an emulated xics.) All interrupts should be disabled when the kernel starts, but this can be observed if a driver does not shutdown an interrupt in its reboot hook before starting a new kernel with kexec. Michael reports this can be reproduced trivially by banging the keyboard while kexec'ing on a P5 LPAR: even though the hvc_console driver request's the console irq later in boot, the console is non-functional because we're receiving no console interrupts. Reported-By: Michael Ellerman Signed-off-by:
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- 10 Oct, 2008 3 commits
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Benjamin Herrenschmidt authored
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Jon Tollefson authored
If there are multiple reserved memory blocks via lmb_reserve() that are contiguous addresses and on different NUMA nodes we are losing track of which address ranges to reserve in bootmem on which node. I discovered this when I recently got to try 16GB huge pages on a system with more then 2 nodes. When scanning the device tree in early boot we call lmb_reserve() with the addresses of the 16G pages that we find so that the memory doesn't get used for something else. For example the addresses for the pages could be 4000000000, 4400000000, 4800000000, 4C00000000, etc - 8 pages, one on each of eight nodes. In the lmb after all the pages have been reserved it will look something like the following: lmb_dump_all: memory.cnt = 0x2 memory.size = 0x3e80000000 memory.region[0x0].base = 0x0 .size = 0x1e80000000 memory.region[0x1].base = 0x4000000000 .size = 0x2000000000 reserved.cnt = 0x5 reserved.size = 0x3e80000000 reserved.region[0x0].base = 0x0 .size = 0x7b5000 reserved.region[0x1].base = 0x2a00000 .size = 0x78c000 reserved.region[0x2].base = 0x328c000 .size = 0x43000 reserved.region[0x3].base = 0xf4e8000 .size = 0xb18000 reserved.region[0x4].base = 0x4000000000 .size = 0x2000000000 The reserved.region[0x4] contains the 16G pages. In arch/powerpc/mm/num.c: do_init_bootmem() we loop through each of the node numbers looking for the reserved regions that belong to the particular node. It is not able to identify region 0x4 as being a part of each of the 8 nodes. It is assuming that a reserved region is only on a single node. This patch takes out the reserved region loop from inside the loop that goes over each node. It looks up the active region containing the start of the reserved region. If it extends past that active region then it adjusts the size and gets the next active region containing it. Signed-off-by:Jon Tollefson <kniht@linux.vnet.ibm.com> Signed-off-by:
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Paul Mackerras authored
Commit 9b09c6d9 ("powerpc: Change the default link address for pSeries zImage kernels") changed the real-base value in the CHRP note added by the addnote program from 12MB to 32MB to give more space for Open Firmware to load the zImage. (The real-base value says where we want OF to position itself in memory.) However, this change was ineffective on most pSeries machines, because the RPA note added by addnote has the "ignore me" flag set to 1. This was intended to tell OF to ignore just the RPA note, but has the side effect of also making OF ignore the CHRP note (at least on most pSeries machines). To solve this we have to set the "ignore me" flag to 0 in the RPA note. (We can't just omit the RPA note because that is equivalent to having an RPA note with default values, and the default values are not what we want.) However, then we have to make sure the values in the zImage's RPA note match up with the values that the kernel supplies later in prom_init.c with either the ibm,client-architecture-support call or the process-elf-header call in prom_send_capabilities(). So this sets the "ignore me" flag in the RPA note in addnote to 0, and adjusts the RPA note values in addnote.c and in prom_init.c to be consistent with each other and with the values in ibm_architecture_vec. However, since the wrapper is independent of the kernel, this doesn't ensure that the notes will stay consistent. To ensure that, this adds code to addnote.c so that it can extract the kernel's RPA note from the kernel binary and put that in the zImage. To that end, we put the kernel's fake ELF header (which contains the kernel's RPA note) into its own section, and arrange for wrapper to pull out that section with objcopy and pass it to addnote, which then extracts the RPA note from it and transfers it to the zImage. Signed-off-by:
Paul Mackerras <paulus@samba.org> Signed-off-by:
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