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  1. 22 May, 2015 3 commits
  3. 21 May, 2015 1 commit
  5. 20 May, 2015 1 commit
    • Mengdong Lin's avatar
      ALSA: hda - Move hda_i915.c from sound/pci/hda to sound/hda · 98d8fc6c
      Mengdong Lin authored 
      The file is moved to hda core and renamed to hdac_i915.c, so can be used
by both legacy HDA driver and new Skylake audio driver.

- Add snd_hdac_ prefix to the public APIs.
- The i915 audio component is moved to core bus and dynamically allocated.
- A static pointer hdac_acomp is used to help bind/unbind callbacks to get
  this component, because the sound card's private_data is used by the azx
  chip pointer, which is a legacy structure. It could be removed if private
  _data changes to some core structure which can be extended to find the
  bus.
- snd_hdac_get_display_clk() is added to get the display core clock for
  HSW/BDW.
- haswell_set_bclk() is moved to hda_intel.c because it needs to write the
  controller registers EM4/EM5, and only legacy HD-A needs it for HSW/BDW.
- Move definition of HSW/BDW-specific registers EM4/EM5 to hda_register.h
  and rename them to HSW_EM4/HSW_EM5, because other HD-A controllers have
  different layout for the extended mode registers.
Signed-off-by: default avatarMengdong Lin <mengdong.lin@intel.com>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
      98d8fc6c
  7. 19 May, 2015 4 commits
  9. 18 May, 2015 16 commits
  11. 12 May, 2015 1 commit
  13. 11 May, 2015 1 commit
  15. 05 May, 2015 3 commits
    • Thierry Reding's avatar
      ALSA: hda/tegra - Fix oops · 3b90f407
      Thierry Reding authored 
      Commit a41d1224 ("ALSA: hda - Embed bus into controller object")
introduced a regression in the Tegra HDA driver that causes the
following oops during boot:

	[    2.333458] Unable to handle kernel NULL pointer dereference at virtual address 000004c4
	[    2.341537] pgd = c0004000
	[    2.344312] [000004c4] *pgd=00000000
	[    2.347898] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
	[    2.353200] Modules linked in:
	[    2.356264] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W       4.1.0-rc2-next-20150505-00344-g8577890defbf #79
	[    2.366682] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
	[    2.372939] task: ee0d8b40 ti: ee0da000 task.ti: ee0da000
	[    2.378336] PC is at azx_bus_init+0x18/0xf4
	[    2.382516] LR is at hda_tegra_probe+0x6c/0x478
	[    2.387043] pc : [<c06156c4>]    lr : [<c061cf00>]    psr: 60000113
	[    2.387043] sp : ee0dbe38  ip : 00000000  fp : 00000000
	[    2.398501] r10: ed874c00  r9 : 000000fd  r8 : 00000000
	[    2.403717] r7 : ed874c10  r6 : 00000000  r5 : 00000000  r4 : ed016810
	[    2.410232] r3 : c08a2ad4  r2 : c08a1ea0  r1 : 00000000  r0 : ed016810
	[    2.416750] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
	[    2.424046] Control: 10c5387d  Table: 8000406a  DAC: 00000015
	[    2.429783] Process swapper/0 (pid: 1, stack limit = 0xee0da210)
	[    2.435778] Stack: (0xee0dbe38 to 0xee0dc000)
	[    2.440129] be20:                                                       00000000 ed016810
	[    2.448297] be40: 00000000 c061cf00 00000000 ee0dbe5c ed8735d0 c0a7bc48 ed02fd50 ed016000
	[    2.456462] be60: c1250164 ed874c10 c0c66bf8 fffffdfb 00000000 000000fd c0b8dc98 c046664c
	[    2.464628] be80: c0466608 c1250164 ed874c10 00000000 c0c66bf8 c0464eb4 ed874c10 c0c66bf8
	[    2.472793] bea0: ed874c44 c0c43458 00000000 c04650d0 00000000 c0c66bf8 c046503c c04633b4
	[    2.480959] bec0: ee11bea4 ed85f390 c0c66bf8 ed017ac0 00000000 c0464634 c0ab2b7c c0c66bf8
	[    2.489125] bee0: c0bfde20 c0c66bf8 c0bfde20 ed01ce40 c0b7b414 c04656e8 c04665b0 c0bfde20
	[    2.497291] bf00: c0bfde20 c0009770 ee0d8b40 c0c02488 60000113 00000000 00000000 00000003
	[    2.505458] bf20: 00000000 c0c02488 60000113 00000000 c0b54598 c0b16a90 ef7fcc57 c0041228
	[    2.513624] bf40: c0a9150c ef7fcc5f 00000006 00000006 00000000 c0bf1fa8 c0bf2354 00000006
	[    2.521790] bf60: c0b8dc90 c0c7c000 c0c7c000 c0b8dc98 00000000 c0b54dd8 00000006 00000006
	[    2.529956] bf80: c0b54598 00000000 00000000 c07ff08c 00000000 00000000 00000000 00000000
	[    2.538122] bfa0: 00000000 c07ff094 00000000 c000f5a0 00000000 00000000 00000000 00000000
	[    2.546286] bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
	[    2.554451] bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 fffff7ff c013f264
	[    2.562624] [<c06156c4>] (azx_bus_init) from [<c061cf00>] (hda_tegra_probe+0x6c/0x478)
	[    2.570535] [<c061cf00>] (hda_tegra_probe) from [<c046664c>] (platform_drv_probe+0x44/0xa4)
	[    2.578879] [<c046664c>] (platform_drv_probe) from [<c0464eb4>] (driver_probe_device+0x174/0x2b8)
	[    2.587739] [<c0464eb4>] (driver_probe_device) from [<c04650d0>] (__driver_attach+0x94/0x98)
	[    2.596172] [<c04650d0>] (__driver_attach) from [<c04633b4>] (bus_for_each_dev+0x6c/0xa0)
	[    2.604342] [<c04633b4>] (bus_for_each_dev) from [<c0464634>] (bus_add_driver+0x148/0x1f0)
	[    2.612597] [<c0464634>] (bus_add_driver) from [<c04656e8>] (driver_register+0x78/0xf8)
	[    2.620593] [<c04656e8>] (driver_register) from [<c0009770>] (do_one_initcall+0x8c/0x1d4)
	[    2.628765] [<c0009770>] (do_one_initcall) from [<c0b54dd8>] (kernel_init_freeable+0x144/0x1e4)
	[    2.637459] [<c0b54dd8>] (kernel_init_freeable) from [<c07ff094>] (kernel_init+0x8/0xe8)
	[    2.645543] [<c07ff094>] (kernel_init) from [<c000f5a0>] (ret_from_fork+0x14/0x34)

This is caused by azx_bus_init() trying to dereference chip->card, which
for the Tegra driver doesn't get initialized until sometime later during
the call to hda_tegra_create().

Fix this by mimicking the behaviour of the Intel driver and defer HDA
bus initialization until right before the call to snd_device_new().

Fixes: a41d1224 ('ALSA: hda - Embed bus into controller object')
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
      3b90f407
    • Lu, Han's avatar
      ALSA: hda - reset display codec when power on · 0a673521
      Lu, Han authored 
      In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power wells,
so it's necessary to reset display audio codecs when power well on, otherwise
display audio codecs will disappear when resume from low power state.
Reset steps when power on:
    enable codec wakeup -> azx_init_chip() -> disable codec wakeup

The callback for codec wakeup enable/disable is in drivers/gpu/drm/i915/.
Signed-off-by: default avatarLu, Han <han.lu@intel.com>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
      0a673521
    • Lu, Han's avatar
      drm/i915/audio: add codec wakeup override enabled/disable callback · 632f3ab9
      Lu, Han authored 
      Add support for enabling codec wakeup override signal to allow
re-enumeration of the controller on SKL after resume from low power state.

In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power
wells, so it's necessary to reset display audio codecs when power well on,
otherwise display audio codecs will disappear when resume from low power
state.
Reset steps when power on:
    enable codec wakeup -> azx_init_chip() -> disable codec wakeup

v3 by Jani: Simplify to only support toggling the appropriate chicken bit.

v4 by Han: add explanation and specify the hw swquence.
Signed-off-by: default avatarLu, Han <han.lu@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
      632f3ab9
  17. 02 May, 2015 2 commits
  19. 30 Apr, 2015 5 commits
  21. 29 Apr, 2015 3 commits
    • Takashi Iwai's avatar
      Merge branch 'topic/hda' into for-next · 85abf3ec
      Takashi Iwai authored
      85abf3ec
    • Mengdong Lin's avatar
      ALSA: hda - remove controller dependency on i915 power well for Baytrail/Braswell · 2bd1f73f
      Mengdong Lin authored 
      For Baytrail (Valleyview) and Braswell (Cherryview), only the HDMI codec is
in the display power well while the HD-A controller isn't. So the controller
flag 'need_i915_power' is not set to release the display power after probe,
and the codec flag 'link_power_control" is set to request/release the display
power via bus link_power ops.
Signed-off-by: default avatarMengdong Lin <mengdong.lin@intel.com>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
      2bd1f73f
    • Mengdong Lin's avatar
      ALSA: hda - divide controller and codec dependency on i915 gfx power well · 795614dd
      Mengdong Lin authored 
      This patch can improve power saving for Intel platforms on which only the
display audio codec is in the shared i915 power well:

- Add a flag "need_i915_power" to indicate whether the controller needs the
  i915 power well.

- The driver will always request the i915 power when probing the controller
  and codecs if AZX_DCAPS_I915_POWERWELL is set (either the controller or a
  codec needs this power).

- If the controller needs the i915 power, the power will be held after probe
  until the controller is runtime suspended or S3. If the controller doesn't
  need the power, the power will be released the after probe, and a codec
  that needs the power can request/release the power via bus link_power ops.

Background:
- For Haswell/Broadwell, which has a separate HD-A controller for display audio,
  both the controller and the display codec are in the i915 power well.

- For Baytrail/Braswell, the display and analog audio share the same HDA
  controller and link, and only the display codec is in the i915 power well.

- For Skylake, the display and analog audio share the same HDA controller but
  use separate links. Only the display codec is in the i915 power well. And in
  legacy mode we take the two links as one. So it can follow Baytrail/Braswell.
Signed-off-by: default avatarMengdong Lin <mengdong.lin@intel.com>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
      795614dd
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