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  1. 21 May, 2020 8 commits
  3. 05 May, 2020 32 commits
    • Tero Kristo's avatar
      ARM: OMAP5: Make L4SEC clock domain SWSUP only · e88ba436
      Tero Kristo authored 
      Commit c2ce5fb3 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP5, so do the same change
for OMAP5 also.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      e88ba436
    • Tero Kristo's avatar
      ARM: OMAP4: Make L4SEC clock domain SWSUP only · f18e314a
      Tero Kristo authored 
      Commit c2ce5fb3 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP4, so do the same change
for OMAP4 also.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      f18e314a
    • Tero Kristo's avatar
      ARM: dts: omap5: add DES crypto accelerator node · 189a8739
      Tero Kristo authored 
      OMAP5 contains a single DES crypto accelerator instance. Add node for
this in DT to enable it.

We keep the node disabled for now, as it appears OMAP5 platform is
running out of available DMA channels, and DES is the least interesting
crypto accelerator available on the device.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      189a8739
    • Tero Kristo's avatar
      ARM: dts: omap5: add SHA crypto accelerator node · bf755817
      Tero Kristo authored 
      Add the single available SHA crypto accelerator device for OMAP5 SoC.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      bf755817
    • Tero Kristo's avatar
      ARM: dts: omap5: add aes2 entry · 4b9882ae
      Tero Kristo authored 
      OMAP5 has AES hardware cryptographic accelerator, add AES2 instance for
it.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      4b9882ae
    • Tero Kristo's avatar
      ARM: dts: omap5: add aes1 entry · f9cd51bf
      Tero Kristo authored 
      OMAP5 has AES hardware cryptographic accelerator, add AES1 instance for
it.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      f9cd51bf
    • Suman Anna's avatar
      ARM: dts: dra7-ipu-dsp-common: Add watchdog timers to IPU and DSP nodes · 1f159805
      Suman Anna authored 
      The watchdog timer information has been added to all the IPU and DSP
remote processor device nodes in the DRA7xx/AM57xx SoC families. The
data has been added to the two common dra7-ipu-dsp-common and
dra74-ipu-dsp-common dtsi files that can be included by all the
desired board files. The following timers are chosen as the watchdog
timers, as per the usage on the current firmware images:
        IPU2: GPTimers 4 & 9 (one for each Cortex-M4 core)
        IPU1: GPTimers 7 & 8 (one for each Cortex-M4 core)
        DSP1: GPTimer 10
        DSP2: GPTimer 13

Each of the IPUs has two Cortex-M4 processors and so uses a timer
each for providing watchdog support on that processor irrespective of
whether the IPU is running in SMP-mode or non-SMP node. The chosen
timers also need to be unique from the ones used by other processors
(regular timers or watchdog timers) so that they can be supported
simultaneously.

The MPU-side drivers will use this data to initialize the watchdog
timer(s), and listen for any watchdog triggers. The BIOS-side code on
these processors needs to configure/refresh the corresponding timer
properly to not throw a watchdog error.

The watchdog timers are optional in general, but are mandatory to
be added to support watchdog error recovery on a particular processor.
These timers can be changed or removed as per the system integration
needs, alongside appropriate equivalent changes on the firmware side.
Signed-off-by: default avatarAngela Stegmaier <angelabaker@ti.com>
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      1f159805
    • Suman Anna's avatar
      ARM: dts: am571x-idk: Add CMA pools and enable IPUs & DSP1 rprocs · c2a5678e
      Suman Anna authored 
      The CMA reserved memory nodes have been added for both the IPUs and the
DSP1 remoteproc devices on the AM571x IDK board. These nodes are assigned
to the respective rproc device nodes, and both the IPUs and the DSP1
remote processors are enabled for this board.

The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on the
DRA72 EVM board to maintain firmware compatibility between the two boards.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.

An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      c2a5678e
    • Suman Anna's avatar
      ARM: dts: am572x-idk-common: Add CMA pools and enable IPU & DSP rprocs · ac21a4a8
      Suman Anna authored 
      The CMA reserved memory nodes have been added for all the IPU and DSP
remoteproc devices in the am572x-idk-common.dtsi file that is common to
both the AM572x and AM574x IDK boards. These nodes are assigned to the
respective rproc device nodes, and all the IPU and DSP remote processors
are enabled.

The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on
the AM57xx EVM board to maintain firmware compatibility between the
two boards. The CMA pools and sizes are defined using 64-bit values
to support LPAE. The starting addresses are fixed to meet current
dependencies on the remote processor firmwares, and this will go
away when the remote-side code has been improved to gather this
information runtime during its initialization.

An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      ac21a4a8
    • Suman Anna's avatar
      ARM: dts: beagle-x15-common: Add CMA pools and enable IPU & DSP rprocs · 35529cc0
      Suman Anna authored 
      The CMA reserved memory nodes have been added for all the IPU and DSP
remoteproc devices on all the AM57xx BeagleBoard-X15 boards. These nodes
are assigned to the respective rproc device nodes, and all the IPU and
DSP remote processors are enabled for all these boards.

The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on the
DRA7 EVM board to maintain firmware compatibility between the two boards.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.

An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      35529cc0
    • Suman Anna's avatar
      ARM: dts: dra76-evm: Add CMA pools and enable IPU & DSP rprocs · 101a29dd
      Suman Anna authored 
      The CMA reserved memory nodes have been added for all the IPU and
the DSP remoteproc devices on the DRA76 EVM board, and assigned to
the respective rproc device nodes. These match the configuration
used on the DRA7 EVM board. Both the CMA nodes and the corresponding
rproc nodes are also enabled to enable these processors on the
DRA76 EVM board.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      101a29dd
    • Suman Anna's avatar
      ARM: dts: dra71-evm: Add CMA pools and enable IPUs & DSP1 rprocs · f09862d5
      Suman Anna authored 
      The CMA reserved memory nodes have been added for both the IPUs and the
DSP1 remoteproc devices on DRA71 EVM board. These nodes are assigned to
the respective rproc device nodes, and both the IPUs and the DSP1 remote
processors are enabled for this board.

The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on the
DRA72 EVM board to maintain firmware compatibility between the two boards.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.

An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      f09862d5
    • Suman Anna's avatar
      ARM: dts: dra72-evm-revc: Add CMA pools and enable IPUs & DSP1 rprocs · 81fe00fa
      Suman Anna authored 
      The CMA reserved memory nodes have been added for both the IPUs and
the DSP1 remoteproc devices on the DRA72 EVM rev C board, and assigned
to the respective rproc device nodes. These match the configuration
used on the DRA72 EVM board. Both the CMA nodes and the corresponding
rproc nodes are also enabled to enable these processors on the
DRA72 EVM rev C board.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      81fe00fa
    • Suman Anna's avatar
      ARM: dts: dra72-evm: Add CMA pools and enable IPUs & DSP1 rprocs · 791cc4e4
      Suman Anna authored 
      The CMA reserved memory nodes have been added for both the IPUs and the
DSP1 remoteproc devices on DRA72 EVM board. These nodes are assigned to
the respective rproc device nodes, and both the IPUs and the DSP1 remote
processors are enabled for this board.

The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on the
DRA7 EVM board to maintain firmware compatibility between the two boards.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.

An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      791cc4e4
    • Suman Anna's avatar
      ARM: dts: dra7-evm: Add CMA pools and enable IPU & DSP rprocs · 371cddbd
      Suman Anna authored 
      The CMA reserved memory nodes have been added for all the IPU and DSP
remoteproc devices on DRA7 EVM board. These nodes are assigned to the
respective rproc device nodes, and all the IPU and DSP remote processors
are enabled for this board.

The current CMA pools and sizes are defined statically for each device.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.

An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      371cddbd
    • Suman Anna's avatar
      ARM: dts: dra7-ipu-dsp-common: Add timers to IPU and DSP nodes · d329f9f1
      Suman Anna authored 
      The BIOS System Tick timers have been added for all the IPU and
DSP remoteproc devices in the DRA7 SoC family. The data is added
to the two common dra7-ipu-dsp-common and dra74-ipu-dsp-common
dtsi files that are included by all the desired board files. The
following timers are chosen, as per the timers used on the current
firmware images:
        IPU2: GPTimer 3
        IPU1: GPTimer 11
        DSP1: GPTimer 5
        DSP2: GPTimer 6

The timers are optional, but are mandatory to support advanced device
management features such as power management and watchdog support.
The above are added to successfully boot and execute firmware images
configured with the respective timers, images that use internal
processor subsystem timers are not affected. The timers can be
changed or removed as per the system integration needs, if needed.

Each of the IPUs has two Cortex-M4 processors, and is currently
expected to be running in SMP-mode, so only a single timer suffices
to provide the BIOS tick timer. An additional timer should be added
for the second processor in IPU if it were to be run in non-SMP mode.
The timer value also needs to be unique from the ones used by other
processors so that they can be run simultaneously.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      d329f9f1
    • Suman Anna's avatar
      ARM: dts: dra7-ipu-dsp-common: Add mailboxes to IPU and DSP nodes · 5e89b390
      Suman Anna authored 
      Add the required 'mboxes' property to all the IPU and DSP remote
processors (IPU1, IPU2, DSP1 and DSP2) in the two available common
dtsi files - dra7-ipu-dsp-common and dra74-ipu-dsp-common dtsi files.
The latter file is for platforms having DRA74x/DRA76x/AM572x/AM574x
SoCs which do have a DSP2 processor in addition to the other common
remote processors. The common data is added to the former file, and
the DSP2 only data is added to the latter file.

The mailboxes are required for running the Remote Processor Messaging
(RPMsg) stack between the host processor and each of the remote
processors. Each of the remote processors uses a single sub-mailbox
node, the IPUs are assumed to be running in SMP-mode. The chosen
sub-mailboxes match the values used in the current firmware images.
This can be changed, if needed, as per the system integration needs
after making appropriate changes on the firmware side as well.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      5e89b390
    • Suman Anna's avatar
      ARM: dts: dra7-ipu-dsp-common: Move mailboxes into common files · a11a2f73
      Suman Anna authored 
      The System Mailboxes 5 and 6 and their corresponding child sub-mailbox
(IPC 3.x) nodes are enabled in each of the DRA7xx and AM57xx board
dts files individually at present. These mailboxes enable the Remote
Processor Messaging (RPMsg) communication stack between the MPU host
processor and each of the IPU1, IPU2, DSP1 and DSP2 remote processors.

Move these nodes into two common dtsi files - dra7-ipu-dsp-common and
dra74-ipu-dsp-common files, which are then included in various board
dts files. These files can be used to add all the common configuration
properties (except memory data) required by remote processor nodes.
The memory pools and the remote processor nodes themselves are to be
enabled in the actual board dts files. The first file is to used by
platforms using DRA72x/DRA71x/AM571x/AM570x SoCs, and the second file
is to be used by platforms using DRA74x/DRA76x/AM572x/AM574x SoCs.
The second file includes the first file and contains additional data
only applicable for DSP2 remote processor.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      a11a2f73
    • Suman Anna's avatar
      ARM: dts: DRA72x: Add aliases for rproc nodes · 0ed073c2
      Suman Anna authored 
      Add aliases for all the 3 remote processor nodes common to
all DRA72x/DRA71x/AM571x/AM570x boards. The aliases uses the
stem "rproc", and are defined in the order of the most common
processors on the DRA72x family. The ids are same as DRA74x
except for the missing DSP2.

The aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      0ed073c2
    • Suman Anna's avatar
      ARM: dts: DRA74x: Add aliases for rproc nodes · c6df6557
      Suman Anna authored 
      Add aliases for all the IPU and DSP remoteproc processor
nodes common to all DRA74x/DRA76x/AM572x/AM574x boards.
The aliases uses the stem "rproc". The aliases are defined
in the order of the most common processors on the DRA74x
family.

The aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      c6df6557
    • Suman Anna's avatar
      ARM: dts: DRA74x: Add DSP2 processor device node · 78aae49a
      Suman Anna authored 
      The DRA7xx family of SoCs can contain upto two identical DSP
processor subsystems. The second DSP processor subsystem is
present only on the DRA74x/DRA76x variants. The processor
device DT node has therefore been added in disabled state for
this processor subsystem in the DRA74x specific DTS file.

NOTE:
1. The node does not have any mailboxes, timers or CMA region
   assigned, they should be added in the respective board dts
   files.
2. The node should also be enabled as per the individual product
   configuration in the corresponding board dts files.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
[t-kristo@ti.com: converted to support ti-sysc from legacy hwmod]
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      78aae49a
    • Suman Anna's avatar
      ARM: dts: DRA7: Add common IPU and DSP nodes · 46ab8238
      Suman Anna authored 
      The DRA7xx family of SOCs have two IPUs and upto two DSP
processor subsystems in general. The IPU processor subsystem
contains dual-core ARM Cortex-M4 processors, while the DSP
processor subsystem is based on the TI's standard TMS320C66x
DSP CorePac core. The IPUs are very similar to those on OMAP5.

Two IPUs and one DSP processor subsystems is the most common
configuration. The processor device DT nodes have been added
for these processor subsystems, with the internal memories
added through 'reg' and 'reg-names' properties. The IPUs only
have an L2 RAM, whereas the DSPs have L1P, L1D and L2 RAM
memories.

NOTE:
1. The nodes do not have any mailboxes, timers or CMA regions
   assigned, they should be added in the respective board dts
   files.
2. The nodes haven been disabled by default and the enabling
   of these nodes is also left to the respective board dts
   files.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
[t-kristo@ti.com: convert to ti-sysc support from legacy hwmod]
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      46ab8238
    • Tero Kristo's avatar
      ARM: dts: dra7: add timer_sys_ck entries for IPU/DSP timers · 5390130f
      Tero Kristo authored 
      With this, the clocksource driver can setup the timers properly.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      5390130f
    • Tony Lindgren's avatar
      Merge branch 'omap-for-v5.8/dt-timer' into omap-for-v5.8/dt · 7cf0bb80
      Tony Lindgren authored
      7cf0bb80
    • Lokesh Vutla's avatar
      ARM: dts: Add 32KHz clock as default clock source · ac819eda
      Lokesh Vutla authored 
      Clocksource to timer configured in pwm mode can be selected using the DT
property ti,clock-source. There are few pwm timers which are not
selecting the clock source and relying on default value in hardware or
selected by driver. Instead of relying on default value, always select
the clock source from DT.
Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      ac819eda
    • Andrew Jeffery's avatar
      ARM: dts: aspeed: Change KCS nodes to v2 binding · fa4c8ec6
      Andrew Jeffery authored 
      Fixes the following warnings for both g5 and g6 SoCs:

    arch/arm/boot/dts/aspeed-g5.dtsi:376.19-381.8: Warning
    (unit_address_vs_reg): /ahb/apb/lpc@1e789000/lpc-bmc@0/kcs1@0: node
    has a unit name, but no reg property
Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
      fa4c8ec6
    • Eddie James's avatar
      ARM: dts: Aspeed: AST2600: Add XDMA PCI-E root control reset · f90fe8d3
      Eddie James authored 
      The AST2600 XDMA engine requires the PCI-E root control reset be cleared
as well, so add a phandle to that syscon reset.
Signed-off-by: default avatarEddie James <eajames@linux.ibm.com>
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
      f90fe8d3
    • Eddie James's avatar
      ARM: dts: aspeed: ast2600: Add XDMA Engine · e7d1ed84
      Eddie James authored 
      Add a node for the XDMA engine with all the necessary information.
Signed-off-by: default avatarEddie James <eajames@linux.ibm.com>
Reviewed-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
      e7d1ed84
    • Eddie James's avatar
      ARM: dts: aspeed: ast2500: Add XDMA Engine · 910f65c5
      Eddie James authored 
      Add a node for the XDMA engine with all the necessary information.
Signed-off-by: default avatarEddie James <eajames@linux.ibm.com>
Reviewed-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
      910f65c5
    • Manikandan Elumalai's avatar
      ARM: dts: aspeed: Adding Facebook Yosemite V2 BMC · 266056d3
      Manikandan Elumalai authored 
      The Yosemite V2 is a facebook multi-node server
platform that host four OCP server. The BMC
in the Yosemite V2 platform based on AST2500 SoC.

This patch adds linux device tree entry related to
Yosemite V2 specific devices connected to BMC SoC.
Signed-off-by: default avatarManikandan Elumalai <manikandan.hcl.ers.epl@gmail.com>
Acked-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Reviewed-by: default avatarVijay Khemka <vkhemka@fb.com>
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
      266056d3
    • Alexander Filippov's avatar
      ARM: dts: aspeed: Add YADRO Nicole BMC · 697538bd
      Alexander Filippov authored 
      Nicole is an OpenPower machine with an Aspeed 2500 BMC SoC manufactured
by YADRO.
Signed-off-by: default avatarAlexander Filippov <a.filippov@yadro.com>
Acked-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Reviewed-by: default avatarPatrick Williams <patrick@stwcx.xyz>
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
      697538bd
    • Ben Pai's avatar
      ARM: dts: aspeed: mihawk: add aliases for i2c · 6456bc88
      Ben Pai authored 
      Set the bus id for each mux channel to avoid switching channels
multiple times
Signed-off-by: default avatarBen Pai <Ben_Pai@wistron.com>
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
      6456bc88
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