- 01 Sep, 2017 15 commits
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Quentin Schulz authored
This allows gclk to determine audio_pll rate and set the parent rate accordingly. However, there are multiple children clocks that could technically change the rate of audio_pll (via gck). With the rate locking, the first consumer to enable the clock will be the one definitely setting the rate of the clock. Since audio IPs are most likely to request the same rate, we enforce that the only clks able to modify gck rate are those of audio IPs. To remain consistent, we deny other clocks to be children of audio_pll. Signed-off-by:
Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Quentin Schulz authored
The way to find the best_diff and do the appropriate process afterwards can be re-used. This patch prepares the driver for an upcoming patch that will allow clk_generated to determine the rate of the audio_pll. Signed-off-by:
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Quentin Schulz authored
This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications. The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formulas, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz. Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Quentin Schulz authored
This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications. The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formulas, they are handled by two different drivers. This adds the audio plls (frac, pad and pmc) to the compatible list of at91 clocks in DT binding. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
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Quentin Schulz authored
The driver requests the current clk rate of each of its parent clocks to decide whether a clock rate is suitable or not. It does not request determine_rate from a parent clock which could request a rate change in parent clock (i.e. there is no parent rate propagation). We know the rate we want (passed along req argument of the function) and the parent clock rate, thus we know the closest rounded divisor, we don't need to iterate over the available divisors to find the best one for a given clock. Signed-off-by:
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Andreas Färber authored
It fails to build once we introduce the ARCH_MB86S7X Kconfig symbol: drivers/clk/clk-mb86s7x.c:27:10: fatal error: soc/mb86s7x/scb_mhu.h: No such file or directory #include <soc/mb86s7x/scb_mhu.h> ^~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. And when commenting out that line, we get: drivers/clk/clk-mb86s7x.c: In function 'crg_gate_control': drivers/clk/clk-mb86s7x.c:72:8: error: implicit declaration of function 'mb86s7x_send_packet' [-Werror=implicit-function-declaration] ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ, ^~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:72:28: error: 'CMD_PERI_CLOCK_GATE_SET_REQ' undeclared (first use in this function) ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ, ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:72:28: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/clk-mb86s7x.c: In function 'crg_rate_control': drivers/clk/clk-mb86s7x.c:116:10: error: 'CMD_PERI_CLOCK_RATE_SET_REQ' undeclared (first use in this function) code = CMD_PERI_CLOCK_RATE_SET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:121:10: error: 'CMD_PERI_CLOCK_RATE_GET_REQ' undeclared (first use in this function); did you mean 'CMD_PERI_CLOCK_RATE_SET_REQ'? code = CMD_PERI_CLOCK_RATE_GET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~~ CMD_PERI_CLOCK_RATE_SET_REQ drivers/clk/clk-mb86s7x.c: In function 'mhu_cluster_rate': drivers/clk/clk-mb86s7x.c:276:10: error: 'CMD_CPU_CLOCK_RATE_GET_REQ' undeclared (first use in this function) code = CMD_CPU_CLOCK_RATE_GET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:278:10: error: 'CMD_CPU_CLOCK_RATE_SET_REQ' undeclared (first use in this function); did you mean 'CMD_CPU_CLOCK_RATE_GET_REQ'? code = CMD_CPU_CLOCK_RATE_SET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~ CMD_CPU_CLOCK_RATE_GET_REQ cc1: some warnings being treated as errors scripts/Makefile.build:302: recipe for target 'drivers/clk/clk-mb86s7x.o' failed make[2]: *** [drivers/clk/clk-mb86s7x.o] Error 1 Remove the driver for now. Signed-off-by:Andreas Färber <afaerber@suse.de> Signed-off-by:
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Colin Ian King authored
strrchr can potentially return a null so the following strlen on the null pointer can cause a null dereference. Add a check to see if the string postfix is not null before calling strlen. Detected by CoverityScan, CID#1452039 ("Dereference null return") Signed-off-by:Colin Ian King <colin.king@canonical.com> Acked-by:
Tero Kristo <t-kristo@ti.com> Signed-off-by:
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Alex Frid authored
Add a check for error returned by divider value calculation to avoid writing error code into hw register. Signed-off-by:
Alex Frid <afrid@nvidia.com> Reviewed-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by:
Jon Mayo <jmayo@nvidia.com> Fixes: bca9690b ("clk: divider: Make generic for usage elsewhere") Signed-off-by:
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Katsuhiro Suzuki authored
Add a clock for video input subsystem (EXIV) on UniPhier LD11/LD20 SoCs. Signed-off-by:
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Katsuhiro Suzuki authored
Add clock for audio subsystem (AIO) and SoC internal audio codec (EVEA) on UniPhier LD11/LD20 SoCs. Signed-off-by:
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Gabriel Fernandez authored
This patch enables clocks for STM32H743 boards. Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@st.com> for MFD changes: Acked-by:
Lee Jones <lee.jones@linaro.org> for DT-Bindings Acked-by:
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Gabriel Fernandez authored
This patch exposes clk_gate_ops::is_enabled as functions that can be directly called and assigned in places like this so we don't need wrapper functions that do nothing besides forward the call. Signed-off-by:
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Gabriel Fernandez authored
We need to export clk_gate_is_enabled() from clk framework, then to avoid compilation issue we have to rename clk_gate_is_enabled() in NXP LPC32xx clock driver. We changed all gate op with 'lpc32xx_' prefix: lpc32xx_clk_gate_enable(), lpc32xx_clk_gate_disable(), lpc32xx_clk_gate_is_enabled(). Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com> Signed-off-by:
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Masahiro Yamada authored
Add basic clock data for Socionext's new SoC PXs3. Signed-off-by:
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Leo Yan authored
The old code uses tcxo (19.2MHz) as watchdog clock but actually the watchdog uses 32K clock, as result the watchdog timeout cannot be set correctly and delay long time to reset SoC. So this patch is to use 'ref32k' as clock source for watchdog. Fixes: 72ea4861 ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC") Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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- 31 Aug, 2017 14 commits
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Elaine Zhang authored
The RK808 and RK805 PMICs are using a similar register map. We can reuse the clk driver for the RK805 PMIC. So let's add the RK805 in the Kconfig description. Signed-off-by:
Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by:
Joseph Chen <chenjh@rock-chips.com> Signed-off-by:
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Gaku Inami authored
This patch adds the common function to reset the clk rate in order to be able to use it in other cases. Signed-off-by:
Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by:
Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by:
Yoshihiro Kaneko <ykaneko0929@gmail.com> Acked-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Lucas Stach authored
This propagates rate requests from the display interface to the divider or PLL output, allowing to hit the required display rate in many more cases. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Tested-By:
Wladimir J. van der Laan <laanwj@gmail.com> Signed-off-by:
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull more Allwinner clock changes from Maxime Ripard: * Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework * tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Add sun4i/sun7i CCU driver dt-bindings: List devicetree binding for the CCU of Allwinner A10 dt-bindings: List devicetree binding for the CCU of Allwinner A20
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Arnd Bergmann authored
gcc-8 reports an uninitialized variable access in a code path that we would see with incorrect DTB input: drivers/clk/sunxi/clk-sun8i-bus-gates.c: In function 'sun8i_h3_bus_gates_init': drivers/clk/sunxi/clk-sun8i-bus-gates.c:85:27: error: 'clk_parent' may be used uninitialized in this function [-Werror=maybe-uninitialized] This works around by skipping invalid input and printing a warning instead if it ever happens. The problem was apparently part of the initiali driver submission, but older compilers don't notice it. Fixes: ab6e23a4 ("clk: sunxi: Add H3 clocks support") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Bhumika Goyal authored
Make this const as it is only stored in the const field of a clk_init_data structure. Signed-off-by:
Bhumika Goyal <bhumirks@gmail.com> Acked-by:
Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by:
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Eugeniy Paltsev authored
HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by:
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by:
Vineet Gupta <vgupta@synopsys.com> Signed-off-by:
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Arvind Yadav authored
clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
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Arvind Yadav authored
clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by:
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Kunihiko Hayashi authored
Add clock control for ethernet controller on Pro4, PXs2, LD11 and LD20. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by:
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Linus Walleij authored
This bit is pin control, and needs to be carefully managed by the new pin control driver. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Arvind Yadav authored
clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_prcc" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_prcc non-const clk_ops argument as const. Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
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Arvind Yadav authored
clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_sysctrl" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_sysctrl non-const clk_ops argument as const. Signed-off-by:
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Arvind Yadav authored
clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_prcmu" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_prcmu non-const clk_ops argument as const. Signed-off-by:
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- 24 Aug, 2017 3 commits
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Priit Laes authored
Introduce a clock controller driver for sun4i A10 and sun7i A20 series SoCs. Signed-off-by:
Priit Laes <plaes@plaes.org> Signed-off-by:
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Priit Laes authored
Allwinner A10 is now driven by sunxi-ng CCU driver. Add devicetree binding for it. Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Priit Laes authored
Allwinner A20 is now driven by sunxi-ng CCU driver. Add devicetree binding for it. Acked-by:
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- 23 Aug, 2017 8 commits
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Srinivas Kandagatla authored
This patch adds missing LPASS smmu clks which are required by the audio driver. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
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Alex Frid authored
- Added necessary delays in PLLU enable sequence during initialization - Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were missing). Signed-off-by:
Thierry Reding <treding@nvidia.com> Acked-by:
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Alex Frid authored
Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us). Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT and ENABLE_DLY_COUNT fields. Signed-off-by:
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Alex Frid authored
Switched Tegra210 PLLRE registration to common PLL ops instead of special PLLRE ops used on previous Tegra chips. The latter ops do not follow chip specific PLL frequency table, and do not apply chip specific rate calculation method. Removed unnecessary default rate setting that duplicates h/w reset state, and is overwritten by clock initialization, anyway. Signed-off-by:
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Alex Frid authored
Remove from Tegra210 PLLSS registration code sections that - attempt to set PLL minimum rate (unnecessary, and dangerous if PLL is already enabled on boot) - apply pre-Tegra210 defaults settings - check IDDQ setting (duplicated with Tegra210 PLLSS check defaults) Replaced setting of reference clock with check that default oscillator selection is not changed, and failed registration otherwise as validation was only done with the oscillator as the reference clock. Reordered registration, so that PLL initialization is called after VCOmin adjustment. Signed-off-by:
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Alex Frid authored
Tegra210 PLLX uses the same sequences than then PLLC instances. So there is no need to have a special registration function and ops struct for it. Simplify the code by changing all references to the Tegra210 PLLX registration function to the Tegra210 PLLC registration function and avoid duplicate functionality. Based on work by Alex Frid <afrid@nvidia.com> Signed-off-by:
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Peter De Schrijver authored
If the PLL is on, only warn if the defaults are not yet set. Otherwise be silent. Signed-off-by:
Timo Alho <talho@nvidia.com> Tested-by:
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Peter De Schrijver authored
Increase delay after PLL IDDQ release to 5us per PLL specifications. based on work by Alex Frid <afrid@nvidia.com> Signed-off-by:
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