- 12 Dec, 2018 26 commits
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kbuild test robot authored
drivers/phy/ti/phy-gmii-sel.c:91:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 1811851f4e73 ("phy: ti: introduce phy-gmii-sel driver") CC: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Maxime Ripard authored
The MIPI D-PHY spec defines default values and boundaries for most of the parameters it defines. Introduce helpers to help drivers get meaningful values based on their current parameters, and validate the boundaries of these parameters if needed. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Maxime Ripard authored
Now that we have some infrastructure for it, allow the MIPI D-PHY phy's to be configured through the generic functions through a custom structure added to the generic union. The parameters added here are the ones defined in the MIPI D-PHY spec, plus the number of lanes in use. The current set of parameters should cover all the potential users. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Maxime Ripard authored
The phy framework is only allowing to configure the power state of the PHY using the init and power_on hooks, and their power_off and exit counterparts. While it works for most, simple, PHYs supported so far, some more advanced PHYs need some configuration depending on runtime parameters. These PHYs have been supported by a number of means already, often by using ad-hoc drivers in their consumer drivers. That doesn't work too well however, when a consumer device needs to deal with multiple PHYs, or when multiple consumers need to deal with the same PHY (a DSI driver and a CSI driver for example). So we'll add a new interface, through two funtions, phy_validate and phy_configure. The first one will allow to check that a current configuration, for a given mode, is applicable. It will also allow the PHY driver to tune the settings given as parameters as it sees fit. phy_configure will actually apply that configuration in the phy itself. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Maxime Ripard authored
MIPI D-PHY is a MIPI standard meant mostly for display and cameras in embedded systems. Add a mode for it. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Li Jun authored
This is a cleaned up port of the downstream i.MX8MQ USB3 PHY driver. Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Lucas Stach authored
This adds the binding for the USB3 PHY found on the i.MX8M SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Rob Herring authored
Convert string compares of DT node names to use of_node_name_eq helper instead. This removes direct access to the node name pointer. For instances using of_node_cmp, this has the side effect of now using case sensitive comparisons. This should not matter for any FDT based system which all of these are. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Grygorii Strashko authored
Add support for port interface mode selection phy (phy-gmii-sel): - try to request interface mode selection phy from Port DT node and fail silently if not defined and old CONFIG_TI_CPSW_PHY_SEL driver enabled. - use new phy if requested successfully. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Grygorii Strashko authored
The cpsw-phy-sel driver was replaced with new PHY driver phy-gmii-sel, so deprecate cpsw-phy-sel bindings and update CPSW binding to use phy-gmii-sel PHY bindings. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Grygorii Strashko authored
TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces. The interface mode is selected by configuring the MII mode selection register(s) (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and bit fields placement in SCM are different between SoCs while fields meaning is the same. Historically CPSW external Port's interface mode selection configuration was introduced using custom API and driver cpsw-phy-sel.c. This leads to unnecessary driver, DT binding and custom API support effort. This patch introduces CPSW Port's PHY Interface Mode selection Driver (phy-gmii-sel) which implements standard Linux PHY interface and used as a replacement for TI's specific driver cpsw-phy-sel.c and corresponding custom API. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Grygorii Strashko authored
Add CPSW Port's Interface Mode Selection PHY (phy-gmii-sel) DT Bindings Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Miquel Raynal authored
Rename the mvebu_comhy_conf structure to be mvebu_comphy_conf, which is probably what the original author meant. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Tony Lindgren authored
I noticed that phy_pm_runtime_get_sync() and phy_pm_runtime_put() are not currently doing anything for phy-mapphone-mdm6600, only the sysfs interface for works for "auto" and "on". This is because of the shared GPIO pins between mdm6600 USB port and n_gsm port. We have not enabled runtime PM for the phy driver until after we've booted up mdm6600 properly to the USB mode. Otherwise phy_create() would have called pm_runtime_enable() and pm_runtime_no_callbacks() automatically on init. Let's fix this by registering the phy a bit later after we've powered up the mdm6600 USB port. And as the PM runtime support is only needed for the n_gsm mode and not for USB, we can allow the device to idle between phy_mdm6600_power_on() and phy_mdm6600_power_off(). Note that for suspend, runtime_pm is already disabled for the phy so we need to check for pm_runtime_enabled(). Cc: Johan Hovold <jhovold@gmail.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Yoshihiro Shimoda authored
This patch modifies rcar_gen3_init_otg() procedure to follow Figure 73.4 of "R-Car Series, 3rd Generation User's Manual: Hardware Rev.1.00". Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Alan Douglas authored
Add a Sierra PHY driver with PCIe and USB support. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Alan Douglas authored
Add DT binding documentation for Sierra PHY. The PHY supports a number of different protocols, including PCIe and USB. The PHY lanes may be configured as single or multi-lane links. Each link is treated as a separate sub-node. For example, if there are 4 lanes in total the first 2 might be configured as a multi-lane PCIe link while the other two are single lane USB links, and in this case there would be 3 sub-nodes. There are two resets for the PHY block (one for APB register access, one for the PHY link) and separate resets for each link. For multi-lane links, the reset corresponds to the reset line on the master lane, the resets on other lanes have no effect. Signed-off-by: Alan Douglas <adouglas@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Grygorii Strashko authored
After recent changes PHY_MODE_SGMII, PHY_MODE_2500SGMII, PHY_MODE_QSGMII, PHY_MODE_10GKR are not used any more and can be removed. Hence - remove them. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Grygorii Strashko authored
Convert mvebu-cp110-comphy PHY driver to use recently introduced PHY_MODE_ETHERNET and phy_set_mode_ext(). Cc: Russell King - ARM Linux <linux@armlinux.org.uk> Cc: Maxime Chevallier <maxime.chevallier@bootlin.com> Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Grygorii Strashko authored
Convert ocelot-serdes PHY driver to use recently introduced PHY_MODE_ETHERNET and phy_set_mode_ext(). Cc: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com> Tested-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Grygorii Strashko authored
Add new PHY's mode to be used by Ethernet PHY interface drivers or multipurpose PHYs like serdes. It will be reused in further changes. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Grygorii Strashko authored
Currently the attempt to add support for Ethernet interface mode PHY (MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and duplicate there values from phy_interface_t enum (or introduce more PHY callbacks) [1]. Both approaches are ineffective and would lead to fast bloating of enum phy_mode or struct phy_ops in the process of adding more PHYs for different subsystems which will make them unmaintainable. As discussed in [1] the solution could be to introduce dual level PHYs mode configuration - PHY mode and PHY submode. The PHY mode will define generic PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem specific interface mode. The last is usually already defined in corresponding subsystem headers (phy_interface_t for Ethernet, enum usb_device_speed for USB). This patch is cumulative change which refactors PHY framework code to support dual level PHYs mode configuration - PHY mode and PHY submode. It extends .set_mode() callback to support additional parameter "int submode" and converts all corresponding PHY drivers to support new .set_mode() callback declaration. The new extended PHY API int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) is introduced to support dual level PHYs mode configuration and existing phy_set_mode() API is converted to macros, so PHY framework consumers do not need to be changed (~21 matches). [1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.comSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Rob Herring authored
DT bindings normally go in via subsystem maintainers, so add PHY bindings under generic PHY framework. Reported-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Icenowy Zheng authored
The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner SoCs, with some USB0 quirk like A83T and PHY index 1/2 missing. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Icenowy Zheng authored
The new Allwinner H6 SoC's USB2 PHY has two holes -- USB1 (which is a 3.0 port with dedicated PHY) and USB2 (which doesn't exist at all). Add support for this kind of missing USB PHY index. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Icenowy Zheng authored
The USB2.0 PHY on Allwinner H6 is similar to the ones on the ones on older SoCs, but with holes in PHY number (USB1 and USB2 are missing, in which USB1 is a USB3 PHY). Add binding for the PHY. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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- 21 Nov, 2018 2 commits
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Manu Gautam authored
Tune1 register on sdm845 is used to update HSTX_TRIM with fused setting. Enable same by specifying update_tune1_with_efuse flag for sdm845, otherwise driver ends up programming tune2 register. Fixes: ef17f6e2 ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845") Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Manu Gautam authored
Fix HSTX_TRIM tuning logic which instead of using fused value as HSTX_TRIM, incorrectly performs bitwise OR operation with existing default value. Fixes: ca04d9d3 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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- 12 Nov, 2018 2 commits
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Douglas Anderson authored
Digging through the "phy-qcom-qmp" showed me many inconsistencies between the bindings and the reality of the driver. Let's fix them all. * In commit 2d66eab1 ("dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074") we probably should have explicitly listed that there are no clocks for this PHY and also added the reset names in alphabetical order. You can see that there are no clocks in the driver where "clk_list" is NULL. * In commit 8587b220 ("dt-bindings: phy-qcom-qmp: Update bindings for QMP V3 USB PHY") we probably should have listed the resets for this new PHY and also removed the "(Optional)" marking for the "cfg" reset since PHYs that need "cfg" really do need it. It's just that not all PHYs need it. * In commit 7f080207 ("dt-bindings: phy-qcom-qmp: Update bindings for sdm845") we forgot to update one instance of the string "qcom,qmp-v3-usb3-phy" to be "qcom,sdm845-qmp-usb3-phy". Let's fix that. We should also have added "qcom,sdm845-qmp-usb3-uni-phy" to the clock-names and reset-names lists. * In commit 99c7c736 ("dt-bindings: phy-qcom-qmp: Add UFS phy compatible string for sdm845") we should have added the set of clocks and resets for "qcom,sdm845-qmp-ufs-phy". These were taken from the driver. * Cleanup the wording for what properties child nodes have to make it more obvious which types of PHYs need clocks and resets. This was sorta implicit in the "-names" description but I found myself confused. * As per the code not all "pcie qmp phys" have resets. Specifically note that the "has_lane_rst" property in the driver is false for "ipq8074-qmp-pcie-phy". Thus make it clear exactly which PHYs need child nodes with resets. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Kunihiko Hayashi authored
The driver uses devm_ioremap_resource() which is only available when CONFIG_HAS_IOMEM is set, so the driver depends on this option. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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- 04 Nov, 2018 9 commits
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Linus Torvalds authored
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git://git.infradead.org/linux-ubifsLinus Torvalds authored
Pull UBIFS updates from Richard Weinberger: - Full filesystem authentication feature, UBIFS is now able to have the whole filesystem structure authenticated plus user data encrypted and authenticated. - Minor cleanups * tag 'tags/upstream-4.20-rc1' of git://git.infradead.org/linux-ubifs: (26 commits) ubifs: Remove unneeded semicolon Documentation: ubifs: Add authentication whitepaper ubifs: Enable authentication support ubifs: Do not update inode size in-place in authenticated mode ubifs: Add hashes and HMACs to default filesystem ubifs: authentication: Authenticate super block node ubifs: Create hash for default LPT ubfis: authentication: Authenticate master node ubifs: authentication: Authenticate LPT ubifs: Authenticate replayed journal ubifs: Add auth nodes to garbage collector journal head ubifs: Add authentication nodes to journal ubifs: authentication: Add hashes to index nodes ubifs: Add hashes to the tree node cache ubifs: Create functions to embed a HMAC in a node ubifs: Add helper functions for authentication support ubifs: Add separate functions to init/crc a node ubifs: Format changes for authentication support ubifs: Store read superblock node ubifs: Drop write_node ...
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git://git.linux-nfs.org/projects/trondmy/linux-nfsLinus Torvalds authored
Pull NFS client bugfixes from Trond Myklebust: "Highlights include: Bugfix: - Fix build issues on architectures that don't provide 64-bit cmpxchg Cleanups: - Fix a spelling mistake" * tag 'nfs-for-4.20-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs: NFS: fix spelling mistake, EACCESS -> EACCES SUNRPC: Use atomic(64)_t for seq_send(64)
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull more timer updates from Thomas Gleixner: "A set of commits for the new C-SKY architecture timers" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: dt-bindings: timer: gx6605s SOC timer clocksource/drivers/c-sky: Add gx6605s SOC system timer dt-bindings: timer: C-SKY Multi-processor timer clocksource/drivers/c-sky: Add C-SKY SMP timer
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git://github.com/jonmason/ntbLinus Torvalds authored
Pull NTB updates from Jon Mason: "Fairly minor changes and bug fixes: NTB IDT thermal changes and hook into hwmon, ntb_netdev clean-up of private struct, and a few bug fixes" * tag 'ntb-4.20' of git://github.com/jonmason/ntb: ntb: idt: Alter the driver info comments ntb: idt: Discard temperature sensor IRQ handler ntb: idt: Add basic hwmon sysfs interface ntb: idt: Alter temperature read method ntb_netdev: Simplify remove with client device drvdata NTB: transport: Try harder to alloc an aligned MW buffer ntb: ntb_transport: Mark expected switch fall-throughs ntb: idt: Set PCIe bus address to BARLIMITx NTB: ntb_hw_idt: replace IS_ERR_OR_NULL with regular NULL checks ntb: intel: fix return value for ndev_vec_mask() ntb_netdev: fix sleep time mismatch
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull scheduler fixes from Ingo Molnar: "A memory (under-)allocation fix and a comment fix" * 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: sched/topology: Fix off by one bug sched/rt: Update comment in pick_next_task_rt()
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Ingo Molnar: "A number of fixes and some late updates: - make in_compat_syscall() behavior on x86-32 similar to other platforms, this touches a number of generic files but is not intended to impact non-x86 platforms. - objtool fixes - PAT preemption fix - paravirt fixes/cleanups - cpufeatures updates for new instructions - earlyprintk quirk - make microcode version in sysfs world-readable (it is already world-readable in procfs) - minor cleanups and fixes" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: compat: Cleanup in_compat_syscall() callers x86/compat: Adjust in_compat_syscall() to generic code under !COMPAT objtool: Support GCC 9 cold subfunction naming scheme x86/numa_emulation: Fix uniform-split numa emulation x86/paravirt: Remove unused _paravirt_ident_32 x86/mm/pat: Disable preemption around __flush_tlb_all() x86/paravirt: Remove GPL from pv_ops export x86/traps: Use format string with panic() call x86: Clean up 'sizeof x' => 'sizeof(x)' x86/cpufeatures: Enumerate MOVDIR64B instruction x86/cpufeatures: Enumerate MOVDIRI instruction x86/earlyprintk: Add a force option for pciserial device objtool: Support per-function rodata sections x86/microcode: Make revision and processor flags world-readable
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull perf updates and fixes from Ingo Molnar: "These are almost all tooling updates: 'perf top', 'perf trace' and 'perf script' fixes and updates, an UAPI header sync with the merge window versions, license marker updates, much improved Sparc support from David Miller, and a number of fixes" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (66 commits) perf intel-pt/bts: Calculate cpumode for synthesized samples perf intel-pt: Insert callchain context into synthesized callchains perf tools: Don't clone maps from parent when synthesizing forks perf top: Start display thread earlier tools headers uapi: Update linux/if_link.h header copy tools headers uapi: Update linux/netlink.h header copy tools headers: Sync the various kvm.h header copies tools include uapi: Update linux/mmap.h copy perf trace beauty: Use the mmap flags table generated from headers perf beauty: Wire up the mmap flags table generator to the Makefile perf beauty: Add a generator for MAP_ mmap's flag constants tools include uapi: Update asound.h copy tools arch uapi: Update asm-generic/unistd.h and arm64 unistd.h copies tools include uapi: Update linux/fs.h copy perf callchain: Honour the ordering of PERF_CONTEXT_{USER,KERNEL,etc} perf cs-etm: Correct CPU mode for samples perf unwind: Take pgoff into account when reporting elf to libdwfl perf top: Do not use overwrite mode by default perf top: Allow disabling the overwrite mode perf trace: Beautify mount's first pathname arg ...
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull irq fixes from Ingo Molnar: "An irqchip driver fix and a memory (over-)allocation fix" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/irq-mvebu-sei: Fix a NULL vs IS_ERR() bug in probe function irq/matrix: Fix memory overallocation
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- 03 Nov, 2018 1 commit
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Peter Zijlstra authored
With the addition of the NUMA identity level, we increased @level by one and will run off the end of the array in the distance sort loop. Fixed: 051f3ca0 ("sched/topology: Introduce NUMA identity node sched domain") Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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