- 12 Aug, 2019 40 commits
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Huang Rui authored
Add Renoir checks to gfx9 code. Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Huang Rui authored
This patch sets fw load type as direct for renoir for the moment. Will switch to psp when psp is ready. Acked-by:
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Huang Rui authored
Add gfx memory controller support for renoir. Acked-by:
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Huang Rui authored
This patch adds common ip support for renoir. Acked-by:
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Huang Rui authored
This patch adds renoir support for gpu_info firmware and ip block setting. Acked-by:
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Huang Rui authored
This patch adds renoir to amd_asic_type enum and amdgpu_asic_name[]. Acked-by:
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Huang Rui authored
This patch add all renoir header files. v2: clean up headers (Alex) Acked-by:
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Colin Ian King authored
The check on ret is duplicated in two places, it is redundant code. Remove it. Addresses-Coverity: ("Logically dead code") Fixes: b94afb61 ("drm/amd/powerplay: honor hw limit on fetching metrics data for navi10") Reviewed-by:Evan Quan <evan.quan@amd.com> Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Christophe JAILLET authored
This should be 'dce_audio_mask', not 'dce_aduio_mask'. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Alex Deucher authored
It's large and doesn't need contiguous memory. Fixes allocation failures in some cases. v2: kvfree the memory. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Pierre-Eric Pelloux-Prayer authored
The SOC15_REG_OFFSET() macro wasn't used, making the soft recovery fail. v2: use WREG32_SOC15 instead of WREG32 + SOC15_REG_OFFSET Signed-off-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Le Ma authored
Follow patch below: drm/amd/powerplay: re-define smu interface version for smu v11 Signed-off-by:Le Ma <le.ma@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Le Ma authored
Init MC_MGCG/LS flag. Also apply to athub CG. Signed-off-by:
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Le Ma authored
Add 2 mmhub instances CG Signed-off-by:
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Le Ma authored
Follow the hw spec, and no need to consider gfxoff on Arcturus Signed-off-by:
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Le Ma authored
Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before drm/amdgpu: enable gfx clock gating for Arcturus Signed-off-by: -
Tao Zhou authored
feature mask info is enough for rocm tool, "cat /sys/class/drm/card0/device/ras/features" will get the info like this: feature mask: 0x3ffb Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Kenneth Feng authored
change the smu_read_sensor sequence to: asic specific sensor read -> smu v11 specific sensor read -> smu v11 common sensor read Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Le Ma authored
Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Le Ma authored
Init sdma MGCG/LS flag Signed-off-by:
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Le Ma authored
Add ARCTURUS case in sdma set clockgating function Signed-off-by:
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Le Ma authored
Shorten the code with RREG32_SDMA/WREG32_SDMA macro in CG part. Signed-off-by:
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Le Ma authored
Init hdp MGCG/LS flag as Vega20 Signed-off-by:
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Le Ma authored
Add hdp CGLS for Arcturus in set common clockgating function Signed-off-by:
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Le Ma authored
Init gfx MGCG/LS and CGCG/LS flag. Signed-off-by:
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Le Ma authored
Add ARCTURUS case in gfx set clockgating function. No 3d clock on Arcturus. Signed-off-by:
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Tao Zhou authored
enable mmhub ras feature and create sysfs/debugfs node for mmhub Signed-off-by:
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Tao Zhou authored
call mmhub ras query/inject in amdgpu ras Signed-off-by:
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Tao Zhou authored
add amdgpu_mmhub_funcs definition and initialize it, prepare for mmhub ras enablement Signed-off-by:
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Tao Zhou authored
ras sub block index could be passed from shell command Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Guchun Chen authored
Sub_block_index can be passed from user level, so add one check before accessing the array first to prevent array index out of bound problem. Signed-off-by:
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tiancyin authored
update the smu11_driver_if_navi10.h since navi14 smu fw update to 53.12 Reviewed-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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tiancyin authored
[why] navi14 share same defination of smu interface version with navi10, anyone of them update the version may break the other one's version checking. [how] create different version defination, so that they can update their version separately. Reviewed-by:
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Alex Deucher authored
Add the navi14 PCI device id. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Michel Dänzer authored
DC already handles this correctly since amdgpu minor version 31. Bump the minor version again so that xf86-video-amdgpu can take advantage of this working without DC as well now. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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David Francis authored
This file was accidentally added to the driver during Navi promotion Nothing includes it. No makefile attempts to compile it, and it would fail compilation if they tried Remove it Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com>w Signed-off-by:
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Xiaojie Yuan authored
enables vcn medium grained clock gating Signed-off-by:
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Xiaojie Yuan authored
enables athub medium grained clock gating and memory light sleep Signed-off-by:
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Xiaojie Yuan authored
add navi12 define Signed-off-by:
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Xiaojie Yuan authored
enables ih clock gating Signed-off-by:
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