- 19 Apr, 2017 11 commits
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Thomas Petazzoni authored
There is no SPEAr600 device named "adc". Instead, the description of the ADC was recently added to the Device Tree, and the device name is "d820b000.adc", so we should associate the ADC gatable clock to this device name. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Kevin-CW Chen authored
Add MT6797 clock support, include topckgen, apmixedsys, infracfg and subsystem clocks Signed-off-by:
Kevin-CW Chen <kevin-cw.chen@mediatek.com> Signed-off-by:
Mars Cheng <mars.cheng@mediatek.com> Tested-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
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Kevin-CW Chen authored
This patch adds the binding documentation for apmixedsys, imgsys, infracfg, mmsys, topckgen, vdecsys and vencsys for MT6797. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Stephen Boyd authored
* clk-mt6797: clk: mediatek: add mt6797 clock IDs
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Mars Cheng authored
Signed-off-by:
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Dong Aisheng authored
Add the missing ipg_root_clk which actually is already used by many orphan clks in current tree. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Stefan Agner <stefan@agner.ch> Tested-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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Dong Aisheng authored
MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200 used actually is for adc, not ahb. After fix, correct ocram_s_clk parent accordingly as well. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
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Alexey Firago authored
Update IDT VersaClock 5 driver to support 5P49V5935. This chip has two clock inputs (internal XTAL or external CLKIN), four fractional dividers (FODs) and five clock outputs (four universal clock outputs and one reference clock output at OUT0_SELB_I2C). Current driver supports up to 2 FODs and up to 3 clock outputs. This patch sets max number of supported FODs to 4 and max number of supported clock outputs to 5. Signed-off-by:
Alexey Firago <alexey_firago@mentor.com> Reviewed-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
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Alexey Firago authored
IDT VersaClock 5 5P49V5935 has 4 clock outputs, 4 fractional dividers. Input clock source can be taken from either integrated crystal or from external reference clock. Signed-off-by:
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Alexey Firago authored
Introduce vc5_chip_info structure to describe features of a particular VC5 chip (id, number of FODs, number of outputs, flags). For now flags are only used to indicate if chip has internal XTAL. vc5_chip_info is set on probe from the matched of_device_id->data. Also add defines to specify maximum number of FODs and clock outputs supported by the driver. With these changes it should be easier to extend driver to support more VC5 models. Signed-off-by:
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock patches for 4.12 from Maxime Ripard: Support for the new H5 SoC and the PRCM block found in a number of SoCs as well, plus the usual chunk of fixes and minor enhancements. * tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Display index when clock registration fails clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks clk: sunxi-ng: mult: Support PLL lock detection clk: sunxi-ng: add support for PRCM CCUs dt-bindings: update device tree binding for Allwinner PRCM CCUs clk: sunxi-ng: sun5i: Fix mux width for csi clock clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver clk: sunxi-ng: gate: Support common pre-dividers
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- 17 Apr, 2017 2 commits
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Stephen Boyd authored
* clk-fixes: clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
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Stephen Boyd authored
Merge tag 'sunxi-clk-fixes-for-4.11-2-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull Allwinner clock fixes for 4.11 from Maxime Ripard: Two build errors fixes for the sunxi-ng drivers. The two other patches fix random CPU crashes happening on the A33 since CPUFreq has been enabled in 4.11. * tag 'sunxi-clk-fixes-for-4.11-2-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER
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- 13 Apr, 2017 4 commits
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Chen-Yu Tsai authored
This patch utilizes the new PLL clk notifier to gate then ungate the PLL CPU clock after rate changes. This should mitigate the system hangs observed after the introduction of cpufreq for the A33. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Tested-by:
Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
In common PLL designs, changes to the dividers take effect almost immediately, while changes to the multipliers (implemented as dividers in the feedback loop) take a few cycles to work into the feedback loop for the PLL to stablize. Sometimes when the PLL clock rate is changed, the decrease in the divider is too much for the decrease in the multiplier to catch up. The PLL clock rate will spike, and in some cases, might lock up completely. This is especially the case if the divider changed is the pre-divider, which affects the reference frequency. This patch introduces a clk notifier callback that will gate and then ungate a clk after a rate change, effectively resetting it, so it continues to work, despite any possible lockups. Care must be taken to reparent any consumers to other temporary clocks during the rate change, and that this notifier callback must be the first to be registered. This is intended to fix occasional lockups with cpufreq on newer Allwinner SoCs, such as the A33 and the H3. Previously it was thought that reparenting the cpu clock away from the PLL while it stabilized was enough, as this worked quite well on the A31. On the A33, hangs have been observed after cpufreq was recently introduced. With the H3, a more thorough test [1] showed that reparenting alone isn't enough. The system still locks up unless the dividers are limited to 1. A hunch was if the PLL was stuck in some unknown state, perhaps gating then ungating it would bring it back to normal. Tests done by Icenowy Zheng using Ondrej's test firmware shows this to be a valid solution. [1] http://www.spinics.net/lists/arm-kernel/msg552501.htmlReported-by:
Ondrej Jirman <megous@megous.com> Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Tested-by:
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Tobias Regnery authored
The ccu-sun9i-a80 driver uses the ccu_mult_ops struct, but unlike the other users it doesen't select the corresponding Kconfig symbol under which the struct is compiled in. This results in the following link error with CONFIG_SUN9I_A80_CCU=y and CONFIG_SUNXI_CCU_MULT=n: drivers/built-in.o:(.data+0x2d638): undefined reference to 'ccu_mult_ops' Fix this by explicitly selecting CONFIG_SUNXI_CCU_MULT like the other users of the struct. Signed-off-by:
Tobias Regnery <tobias.regnery@gmail.com> Signed-off-by:
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Tobias Regnery authored
With CONFIG_RESET_CONTROLLER=n we get the following link error in the sunxi-ng clk driver: drivers/built-in.o: In function `sunxi_ccu_probe': mux-core.c:(.text+0x12fe68): undefined reference to 'reset_controller_register' mux-core.c:(.text+0x12fe68): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol 'reset_controller_register' Fix this by adding the appropriate select statement. Signed-off-by:
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- 12 Apr, 2017 22 commits
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Kuninori Morimoto authored
Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Michael Turquette <mturquette@baylibre.com>
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git://github.com/BayLibre/clk-mesonMichael Turquette authored
Pull AmLogic clk driver updates from Jerome Brunet: 2nd Amlogic clock driver update for 4.12: * Protect against holes in onecell_data * Fix divison by zero and overflow in the mpll driver * Add audio clock divider driver for i2s clocks * Add i2s and spdif master clocks
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Michael Turquette authored
Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into clk-next Same great taste as the previous pull request, but now with 50% less DT bikeshedding! Amlogic clock driver updates for v4.12 - meson8: add some new PLLs - new clocks for Mali - misc fixes.
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Peter De Schrijver authored
In case there are multiple notify chains for the same clocks (because they were registered by different users), we need to propagate potential failure of any single one of them to the caller. Otherwise we eg risk violating the V/f curve when a notifier is used for DVFS. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
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Peter De Schrijver authored
For validation purposes, it's often useful to be able to retrieve the list of possible parents in userspace. Add a debugfs file for every clock which has more than 1 possible parent. Signed-off-by:
Jon Mayo <jmayo@nvidia.com> [sboyd@codeaurora.org: Remove useless cast from void and extra newline] Signed-off-by:
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Robin van der Gracht authored
Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Robin van der Gracht <robin@protonic.nl> Signed-off-by:
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Stephen Boyd authored
These should be const. Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Jun Nie <jun.nie@linaro.org> Signed-off-by:
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Shawn Guo authored
It adds zx296718 pll_vga clock for VGA support, so that VGA device can get required pixel rate from clock driver for different display mode. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Reviewed-by:
Jun Nie <jun.nie@linaro.org> Signed-off-by:
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Shawn Guo authored
The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of of postdiv2 field. The consequence is that functions like hw_to_idx() and zx_pll_enable() will end up tampering the postdiv2 of the PLL. Let's fix it by defining pd_bit 0xff which is obviously invalid for a bit position and having PLL driver check the validity before operating on the bit. Signed-off-by:
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Shawn Guo authored
To support VOU VGA display driver with different modes, we need to set flag for a few clocks, so that clk_set_rate() call in VOU driver can get VGA device desired pixel rate. While at it, the divider between pll_vga and clk_vga gets corrected, as it's 1:1 instead of 1:2. Signed-off-by:
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Robin van der Gracht authored
The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register. Reviewed-by:
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Michael Turquette authored
Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull Tegra clk driver updates from Thierry Reding: This contains a bunch of fixes and cleanups, mostly to the Tegra210 clock driver. * tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits) clk: tegra: Don't reset PLL-CX if it is already enabled clk: tegra: Add missing Tegra210 clocks clk: tegra: Propagate clk_out_x rate to parent clk: tegra: Fix build warnings on Tegra20/Tegra30 clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on clk: tegra: Add SATA seq input control clk: tegra: Add Tegra210 special resets clk: tegra: Rework pll_u clk: tegra: Implement reset control reset clk: tegra: Fix disable unused for clocks sharing enable bit clk: tegra: Handle UTMIPLL IDDQ clk: tegra: Add aclk clk: tegra: Add super clock mux/divider clk: tegra: Define Tegra210 DMIC clocks clk: tegra: Fix constness for peripheral clocks clk: tegra: Define Tegra210 DMIC sync clocks clk: tegra: Add CEC clock clk: tegra: Fix type for m field clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation clk: tegra: Don't warn for PLL defaults unnecessarily ...
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Kuninori Morimoto authored
Thus CS2000 datasheet is indicating below, this patch follows it. WARNING: All "Reserved" registers must maintain their default state to ensure proper functional operation. Signed-off-by: -
Rajendra Nayak authored
Fix a typo which caused both vfe0 and vfe1 powerdomains to be named as vfe0. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Fixes: 7e824d50 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by:
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Gabriel Fernandez authored
Use a classic polling to test bit ready. And the shift of the bit ready of LSE & LSI were wrongs. Fixes: 861adc44 ("clk: stm32f4: Add LSI & LSE clocks") Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by:
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Ray Jui authored
Remove the redundant check of 'rate' in the if statement of the 'pll_set_rate' function Reported-by:
David Binderman <dcb314@hotmail.com> Signed-off-by:
Ray Jui <ray.jui@broadcom.com> Fixes: 5fe225c1 ("clk: iproc: add initial common clock support") Signed-off-by:
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Michael Turquette authored
Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: General rockchip clock changes for 4.12. Contains some new clock-ids as well as fixups of the clock-ids on rk3368 timers, which were unused and completely wrong (more and differently named timers). Also there is one new clock on rk3328 using the muxgrf type, a fix for pll enablement which should wait for the pll to lock before continuing, some more critical clocks and the rename of the rk1108 to rv1108, as the soc seems to have been using a preliminary name before its actual release. The plan is to have the driver changes (pinctrl, clk) go through the respective maintainer trees and once everything landed in mainline do the rename of the devicetree files. With the dts-include change in the clock rename, we also keep everything compiling and thus bisectability. * tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add pll_wait_lock for pll_enable clk: rockchip: rename RK1108 to RV1108 dt-bindings: rk1108-cru: rename RK1108 to RV1108 clk: rockchip: mark some rk3368 core-clks as critical clk: rockchip: export SCLK_TIMERXX id for timers on rk3368 clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328 clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs clk: rockchip: fix up rk3368 timer-ids clk: rockchip: add rk3328 clk_mac2io_ext ID clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
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Michael Turquette authored
Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the Clock Pulse Generator / Module Standby and Software Reset module on revision ES2.0 of the R-Car H3 SoC, which differs from ES1.x in some areas. - Add IMR clocks for R-Car H3 and M3-W, - Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0, - Small fixes and cleanups. * tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions clk: renesas: cpg-mssr: Add support for fixing up clock tables clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0 clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init() clk: renesas: r8a7796: Reformat core clock table clk: renesas: r8a7795: Reformat core clock table clk: renesas: r8a7796: Correct name of watchdog clock clk: renesas: r8a7795: Correct name of watchdog clock clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs clk: renesas: r8a7796: Add IMR clocks clk: renesas: r8a7795: Add IMR clocks
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Stephen Boyd authored
* clk-fixes: clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
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Gabriel Fernandez authored
0000: PLLQ = 0, wrong configuration 0001: PLLQ = 1, wrong configuration ... 0010: PLLQ = 2 0011: PLLQ = 3 0100: PLLQ = 4 ... 1111: PLLQ = 1 Use divider table to exclude 0 and 1 values. Fixes: 83135ad3 ("clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards") Signed-off-by:
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https://github.com/t-kristo/linux-pmStephen Boyd authored
* 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm: clk: ti: convert to use proper register definition for all accesses clk: ti: dpll44xx: fix clksel register initialization clk: ti: gate: export gate_clk_ops locally clk: ti: divider: add driver internal API for parsing divider data clk: ti: divider: convert TI divider clock to use its own data representation clk: ti: mux: convert TI mux clock to use its internal data representation clk: ti: drop unnecessary MEMMAP_ADDRESSING flag clk: ti: omap4: cleanup unnecessary clock aliases clk: ti: enforce const types on string arrays clk: ti: move omap2_init_clk_clkdm under TI clock driver clk: ti: add clkdm_lookup to the exported functions clk: ti: use automatic clock alias generation framework clk: ti: add API for creating aliases automatically for simple clock types clk: ti: add support for automatic clock alias generation clk: ti: remove un-used definitions from public clk_hw_omap struct
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Leo Yan authored
The debug APB clock is absent in hi6220 driver, so this patch is to add support for it. Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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- 07 Apr, 2017 1 commit
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Martin Blumenstingl authored
On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz. Multiplying this with SDM_DEN results in a value greater than 32bits. This is not a problem on the 64bit Meson GX SoCs, but it may result in undefined behavior on the older 32bit Meson8b SoC. While rate_from_params was only introduced recently to make the math reusable from _round_rate and _recalc_rate the original bug exists much longer. Fixes: 1c50da4f ("clk: meson: add mpll support") Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> [as discussed on the ml, use DIV_ROUND_UP_ULL] Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com>
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