- 11 Jun, 2019 9 commits
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Neil Armstrong authored
The Amlogic G12A has the hwrng module at the end of an unknown "EFUSE" bus. The hwrng is not enabled on the vendor G12A DTs, but is enabled on next generation SM1 SoC family sharing the exact same memory mapping. Let's add the "EFUSE" bus and the hwrng node. This hwrng has been checked with the rng-tools rngtest FIPS tool : rngtest: starting FIPS tests... rngtest: bits received from input: 1630240032 rngtest: FIPS 140-2 successes: 81436 rngtest: FIPS 140-2 failures: 76 rngtest: FIPS 140-2(2001-10-10) Monobit: 10 rngtest: FIPS 140-2(2001-10-10) Poker: 6 rngtest: FIPS 140-2(2001-10-10) Runs: 26 rngtest: FIPS 140-2(2001-10-10) Long run: 34 rngtest: FIPS 140-2(2001-10-10) Continuous run: 0 rngtest: input channel speed: (min=3.784; avg=5687.521; max=19073.486)Mibits/s rngtest: FIPS tests speed: (min=47.684; avg=52.348; max=52.835)Mibits/s rngtest: Program run time: 30000987 microseconds Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
Kevin Hilman <khilman@baylibre.com>
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Jerome Brunet authored
After discussing with Amlogic, the Synopsys GMAC version used by the gx and axg family is the 3.70a. Set this is in DT Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Reviewed-by:
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Neil Armstrong authored
With the X96 Max board using an external Gigabit Ethernet PHY, add the same driver strength to the Ethernet pins as the vendor tree. Signed-off-by:
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Neil Armstrong authored
With the default boot settings, the DDC drive strength is too weak, set the driver-strengh to 4mA to avoid errors on the DDC line. Signed-off-by:
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Jerome Brunet authored
Enable the network interface of the SEI510 which use the internal PHY. Tested-by:
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Jerome Brunet authored
The u200 is the main mother board for the S905D2. It can provide both the internal and external network. However, by default the resistance required for the external RGMII bus are not fitted, so enable the internal PHY. Signed-off-by:
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Jerome Brunet authored
Add the g12a mdio multiplexer which allows to connect to either an external phy through the SoC pins or the internal 10/100 phy Signed-off-by:
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Jerome Brunet authored
Add the ethernet pinctrl settings for RMII, RGMII and internal phy leds Signed-off-by:
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https://github.com/BayLibre/clk-mesonKevin Hilman authored
MPLL50M DT bindings typo fix Meson9 VPU typo fixes # gpg: Signature made Tue 11 Jun 2019 05:02:13 AM PDT # gpg: using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85 # gpg: Good signature from "Jerome Brunet <jbrunet@baylibre.com>" [full] # gpg: aka "Jerome Brunet <jerome@liltaz.com>" [full] # gpg: aka "Jerome Brunet <jerome.brunet@gmail.com>" [full] * tag 'clk-meson-5.2-1-fixes' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
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- 23 May, 2019 1 commit
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Jerome Brunet authored
Add the synopsys ethernet mac controller embedded in the g12a SoC family. Signed-off-by:
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- 21 May, 2019 30 commits
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Jerome Brunet authored
Add the hdmitx glue device linking the SoC audio interfaces to the embedded Synopsys hdmi controller. Signed-off-by:
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Jerome Brunet authored
Add bluetooth vbat and vddio power supplies Signed-off-by:
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Rob Herring authored
Convert Amlogic SoC bindings to DT schema format using json-schema. Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Rob Herring authored
It is best practice to have 1 binding per file, so board level bindings should be separate for various misc SoC bindings. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Signed-off-by:
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Jerome Brunet authored
At the moment the sysnopsys hdmi i2s driver provides a single playback DAI. Add the corresponding sound-dai-cell to the hdmi device node. Signed-off-by:
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Jerome Brunet authored
Add the spdif input device node and the pinctrl definition for this capture interface g12a SoC family Signed-off-by:
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Jerome Brunet authored
Add the pdm device node and the pinctrl definition for this capture interface g12a SoC family Signed-off-by:
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Jerome Brunet authored
Add the devices nodes and pinctrl definitions for the spdif outputs of the g12a SoC family Signed-off-by:
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Jerome Brunet authored
Add the devices and pinctrl definitions for the tdm interfaces of the g12a SoC family. Signed-off-by:
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Jerome Brunet authored
Add the playback and capture memory interfaces of the g12a SoC family. Signed-off-by:
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Jerome Brunet authored
Add the audio DDR memory arbitrer of the g12a SoC family. Signed-off-by:
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Jerome Brunet authored
Add the g12a clock controller dedicated to audio. Signed-off-by:
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Jerome Brunet authored
Add the i2c bus used for RGB led controller. Signed-off-by:
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Jerome Brunet authored
Add the 3 i2c busses present on the u200 reference design. Signed-off-by:
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Guillaume La Roque authored
Add pinctrl and nodes for i2c support on amlogic g12a Signed-off-by:
Guillaume La Roque <glaroque@baylibre.com> Signed-off-by:
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Jerome Brunet authored
Now that the AO clock controller is available, make the uarts of the always-on domain claim the appropriate peripheral clock. Signed-off-by:
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Jerome Brunet authored
Enable eMMC and SDCard on the g12a sei510 board Signed-off-by:
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Jerome Brunet authored
Enable eMMC and SDCard on the g12a u200 board Signed-off-by:
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Jerome Brunet authored
Add port B (sdcard) and port C (eMMC) pinctrl and controllers nodes to the g12a DT. Signed-off-by:
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Jerome Brunet authored
Add sdcard uhs modes up to DDR50 and push eMMC up to 200Mhz With the new tuning method, these modes appear to be stable Signed-off-by:
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Jerome Brunet authored
Add UHS ddr50 mode to the nanopi k2 Signed-off-by:
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Martin Blumenstingl authored
The Ethernet PHY documentation (Documentation/devicetree/bindings/net/phy.txt) states that: If the PHY reports an incorrect ID (or none at all) then the "compatible" list may contain an entry with the correct PHY ID in the form: "ethernet-phy-idAAAA.BBBB" An older version of the documentation suggested that the compatible string can be used when the PHY ID is known. Remove the ethernet-phy-id compatible string and add a comment with the PHY ID instead. This is a no-op on boards which are shipped with the PHY that was listed (= all known cases). However, if a board manufacturer decides to ship a different PHY we will now load and use the correct driver because we ask the PHY to identify itself. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Jerome Brunet authored
Like order boards, order nodes by address then node names then aliases. Signed-off-by:
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Jerome Brunet authored
Like order boards, order nodes by address then node names then aliases. Signed-off-by:
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Jerome Brunet authored
sd highspeed mode make no sense for an eMMC and HS400 is not working at the moment. Signed-off-by:
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Jerome Brunet authored
For some reason the vim2 is missing the clk-gate pinctrl setting all the other board have. Just add this missing bit Signed-off-by:
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Jerome Brunet authored
According the datasheets, emmc v2 chips (gxbb and gxl) don't support more that 100Mhz in UHS-1 SD modes and HS in SDIO. Align the max-frequency to 100MHz for UHS-1 and 50MHz for HS Signed-off-by:
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Jerome Brunet authored
Clk pin does not require bias, data strobe should be pulled low. The rest of the pin (data and cmd) are pulled up. Signed-off-by:
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Jerome Brunet authored
While some 3.3v eMMC 4.0 are available from libretech, Only the 1.8v 5.0 modules are recommended and supported for the aml-s905x-cc. the 1.8v is provided by LDOs on the eMMC card, from vcc 3.3v Signed-off-by:
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Jerome Brunet authored
The eMMC on this board is add-on module which is not mandatory. Removing 'non-removable' property should prevent some errors when booting a board w/o an eMMC module present. Fixes: 72fb2c85 ("ARM64: dts: meson-gxl-s905x-libretech-cc: fixup board definition") Signed-off-by:
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