- 21 Jul, 2020 40 commits
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Alex Deucher authored
Enable SMU i2c bus access for navi1x asics. v2: add missing implementation Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The driver uses it for EEPROM access, but it's just an i2c bus. v2: change the callback name as well. Reviewed-by:
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Alex Deucher authored
There is no longer a ras dependency so it's safe to expose on all boards. Reviewed-by:
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Alex Deucher authored
The driver uses it for EEPROM access, but it's just an i2c bus. Reviewed-by:
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Alex Deucher authored
It's not really ras related. It's just a lock for the bus in general. This removes the ras dependency from the smu i2c bus. Reviewed-by:
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Paweł Gronowski authored
NULL dereference occurs when string that is not ended with space or newline is written to some dpm sysfs interface (for example pp_dpm_sclk). This happens because strsep replaces the tmp with NULL if the delimiter is not present in string, which is then dereferenced by tmp[0]. Reproduction example: sudo sh -c 'echo -n 1 > /sys/class/drm/card0/device/pp_dpm_sclk' Signed-off-by:
Paweł Gronowski <me@woland.xyz> Signed-off-by:
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Qiu Wenbo authored
Avoid kernel crash when vddci_control is SMU7_VOLTAGE_CONTROL_NONE and vddci_voltage_table is empty. It has been tested on Intel Hades Canyon (i7-8809G). Bug: https://bugzilla.kernel.org/show_bug.cgi?id=208489 Fixes: ac7822b0 ("drm/amd/powerplay: add smumgr support for VEGAM (v2)") Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Qiu Wenbo <qiuwenbo@phytium.com.cn> Signed-off-by:
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Jiansong Chen authored
To accommodate VCN instances variance, otherwise it may trigger smu response error for configuration with less instances. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Jiansong Chen authored
It's in accordance with pmfw 65.3.0 for navy_flounder. Signed-off-by:
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Jiansong Chen authored
It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0. Signed-off-by:
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James Zhu authored
Merge vcn firmware shared memory bo into vcn vcpu bo. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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James Zhu authored
This reverts commit 21b704d7. To merge vcn firmware shared memory bo into vcn vcpu bo. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Igor Kravchenko authored
[Why] Implement an interface to obtain plane size caps [How] Add min_width, min_height fields to dc_plane_cap structure. Set values to 16x16 for discrete ASICs, and 64x64 for others. Signed-off-by:
Igor Kravchenko <Igor.Kravchenko@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why&How] Fix build error by protecting code with config guard to enable building amdgpu without CONFIG_DRM_AMD_DC_DCN enabled. This option is disabled by default for allmodconfig. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] Accessing dcn20_add_dsc_to_stream_resource directly causes build failure for configuration which has CONFIG_DRM_AMD_DC_DCN disabled. Fix this by calling the corresponding function exposed via dc resource functions. Signed-off-by:
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Naveed Ashfaq authored
[why] On DCN20, Some features would not be activated when ALLM was turned on. TV seemed to activate only the latest info packet sent, and the ALLM info packet was sent after the VSIF info packet. The packet indices was also inconsistent between DCN10 and DCN20. [how] Change the packet indices of DCN20 to match those of DCN10. This makes them consistent and also makes the vendor info packet be sent after the hfvsif info packet. Signed-off-by:
Naveed Ashfaq <Naveed.Ashfaq@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Anthony Koo authored
Signed-off-by:
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Aurabindo Pillai authored
[Why] dcn20_add_dsc_to_stream_resource is accessed in amdgpu_dm directly. This creates build error for configuration with DCN disabled. [How] Make the function available through a resource pool function so that dcn20 function need not be called directly. Signed-off-by:
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Wenjing Liu authored
[why] The capability fields are reserved for DSC branch only to report the capability related to the branch's DSC decoder. Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Roman Li authored
[Why] With ABM implemented on DMUB the ABM enablement shoudn't be solely rely on dmcu. Otherwise it won't work if dmcu is disabled. [How] 1. Decouple dmcub config copy from dmcu iram copy. 2. Set abm connector property if either dmcu or dmub enabled. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Reza Amini authored
[Why] To support V3 [How] Generate new VSIF for V3 Signed-off-by:
Reza Amini <Reza.Amini@amd.com> Reviewed-by:
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Eryk Brol authored
[why] Need to add new parameters to debugfs logging so we will know what parameters DSC is using for debug purposes. So we are adding a read function in debugfs to read DSC status registers Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Aric Cyr authored
[Why] Scaler vendor confirmed the 5ms was not helpful so no point in keeping it. [How] Revert 5ms delay after setting training pattern. Signed-off-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
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Nirmoy Das authored
For passthrough device, we do baco reset after 1st vm boot so if we disable SMU on 1st VM shutdown baco reset will fail for 2nd vm boot. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Acked-by:
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Chengming Gui authored
outstanding log reaches threshold will trigger IH ring1/2's wptr reported, that will avoid generating interrupts to ring0 too frequent. But if ring1/2's wptr hasn't been increased for a long time, the outstanding log can't reach threshold so that driver can't get latest wptr info and miss some interrupts. v2: squash in warning fix Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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John Clements authored
set xgmi support flag suring nv ip init sequence Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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John Clements authored
do not abort psp asd load sequence for sienna cichlid Reviewed-by:
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Evan Quan authored
Per designs, the swSMU code is separated into four layers. And the typical calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c -> smu_cmn.c. Compile errors will come out for any violations. This can help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c -> amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code. Signed-off-by: -
Evan Quan authored
This can eliminate the cross callings and maintain clear code layer. Signed-off-by:
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Evan Quan authored
These messages are known to be supported by all ASICs. Signed-off-by:
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Evan Quan authored
Considering they can be shared by all ASICs. Signed-off-by:
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Evan Quan authored
To avoid cross calling and maintain clear code layer. Signed-off-by:
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Evan Quan authored
As they are shared by all ASICs. Signed-off-by:
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Evan Quan authored
Maximum code sharing. Signed-off-by:
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Evan Quan authored
Considering they are shared by all ASICs. Signed-off-by:
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Evan Quan authored
We are moving to centralize all feature enablement/support checking and setting APIs in smu_cmn.c. Signed-off-by:
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Evan Quan authored
Considering they are shared by all ASICs. And we are moving to centralize all feature enablement/support checking and setting APIs in smu_cmn.c. Signed-off-by:
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Evan Quan authored
Instead of having each for smu v11 and v12. Signed-off-by:
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Evan Quan authored
Considering it is shared by all ASICs and smu_cmn.c should be the right place. Signed-off-by:
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