- 11 Dec, 2007 32 commits
-
-
Stephen Rothwell authored
Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Paul Mackerras <paulus@samba.org>
-
Stephen Rothwell authored
This is a purely mechanical transformation. Signed-off-by:
-
will schmidt authored
This adds a bit more detail to the xmon SLB output. When the valid bit is set, this displays the ESID and VSID values, as well as decoding the segment size -- 1T or 256M -- and displaying the LLP bits. This supresses the output for any slb entries that contain only zeros. sample output from power6 (1T segment support): 00 c000000008000000 40004f7ca3000500 1T ESID= c00000 VSID= 4f7ca3 LLP:100 01 d000000008000000 4000eb71b0000400 1T ESID= d00000 VSID= eb71b0 LLP: 0 08 0000000018000000 0000c8499f8ccc80 256M ESID= 1 VSID= c8499f8cc LLP: 0 09 00000000f8000000 0000d2c1a8e46c80 256M ESID= f VSID= d2c1a8e46 LLP: 0 10 0000000048000000 0000ca87eab1dc80 256M ESID= 4 VSID= ca87eab1d LLP: 0 43 cf00000008000000 400011b260000500 1T ESID= cf0000 VSID= 11b260 LLP:100 sample output from power5 (notice the non-valid but non-zero entries) 10 0000000008000000 00004fd0e077ac80 256M ESID= 0 VSID= 4fd0e077a LLP: 0 11 00000000f8000000 00005b085830fc80 256M ESID= f VSID= 5b085830f LLP: 0 12 0000000048000000 000052ce99fe6c80 256M ESID= 4 VSID= 52ce99fe6 LLP: 0 13 0000000018000000 000050904ed95c80 256M ESID= 1 VSID= 50904ed95 LLP: 0 14 cf00000008000000 0000d59aca40f500 256M ESID=cf0000000 VSID= d59aca40f LLP:100 15 c000000078000000 000045cb97751500 256M ESID=c00000007 VSID= 45cb97751 LLP:100 Tested on power5 and power6. Signed-Off-By:
Will Schmidt <will_schmidt@vnet.ibm.com> Signed-off-by:
-
Michael Neuling authored
Currently we hardwire the number of SLBs to 64, but PAPR says we should use the ibm,slb-size property to obtain the number of SLB entries. This uses this property instead of assuming 64. If no property is found, we assume 64 entries as before. This soft patches the SLB handler, so it shouldn't change performance at all. Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
so remove a firmware feature test. Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
and it becomes clear that we should use zalloc_maybe_bootmem. Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
and an unnecessary cast. Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
Also remove another unnecessary forward declaration. Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
No semantic changes. Signed-off-by:
-
Stephen Rothwell authored
Signed-off-by:
-
Stephen Rothwell authored
It only needs the iommu_table address. It also makes use of the node name to print error messages. So just pass it the things it needs. This reduces the places that know about the pci_dn by one. Signed-off-by:
-
Nathan Lynch authored
The 'data' member of proc_ppc64_lparcfg is unused, but the lparcfg module's init routine allocates 4K for it. Remove the code which allocates and frees this buffer. Signed-off-by:
Nathan Lynch <ntl@pobox.com> Signed-off-by:
-
Ishizaki Kou authored
Signed-off-by:
Kou Ishizaki <Kou.Ishizaki@toshiba.co.jp> Signed-off-by:
-
Ishizaki Kou authored
This adds support for native CBE on Celleb, that is, without the BEAT hypervisor. Many codes in platforms/cell/ are used in native CBE environment. Signed-off-by:
-
Ishizaki Kou authored
This fixes the following link error with CONFIG_PPC_CELL_NATIVE=y and CONFIG_PPC_CELL_BLADE=n: arch/powerpc/platforms/built-in.o: In function `.cell_setup_arch': setup.c:(.init.text+0xe80): undefined reference to `.mmio_nvram_init' Signed-off-by:
-
Stephen Rothwell authored
so consolidate it into misc.S. Signed-off-by:
-
Michael Ellerman authored
Add for_each_child_of_node() to encapsulate the common idiom of iterating over the children of a device_node. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Acked-by:
-
Stephen Rothwell authored
Also use of_unregister_driver to implement of_unregister_platform_driver. Signed-off-by:
-
- 10 Dec, 2007 1 commit
-
-
Paul Mackerras authored
-
- 07 Dec, 2007 7 commits
-
-
Linus Torvalds authored
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev: libata: kill spurious NCQ completion detection ahci: don't attach if ICH6 is in combined mode ata_piix: add Toshiba Tecra M4 to broken suspend list ahci: fix engine reset failed message
-
Tejun Heo authored
Spurious NCQ completion detection implemented in ahci was incorrect. On AHCI receving and processing FISes and raising interrupts are not interlocked and spurious interrupts are expected. For example, if an interrupt occurs while interrupt handler is running and the running interrupt handler handles the event the new IRQ indicated, after IRQ handler finishes, it will be executed again because IRQ pending bit is set by the new interrupt but there won't be anything to process. Please read the following message for more information. http://article.gmane.org/gmane.linux.ide/26012 This patch... * Removes all spurious IRQ whining from ahci. Spurious NCQ completion detection was completely wrong. Spurious D2H Register FIS taught us that some early drives send spurious D2H Register FIS with I bit set while NCQ commands are in progress but none of recent drives does that and even the ones which show such behavior can do NCQ fine. * Kills all NCQ blacklist entries which were added because of spurious NCQ completions. I tracked down each commit and verified all removed ones are actually added because of spurious completions. WD740ADFD-00NLR1 wasn't deleted but moved upward because the drive not only had spurious NCQ completions but also is slow on sequential data transfers if NCQ is enabled. Maxtor 7V300F0 was added by 0e3dbc01 from Alan Cox. I can only find evidences that the drive only had troubles with spuruious completions by searching the mailing list. This entry needs to be verified and removed if it doesn't have other NCQ related problems. Signed-off-by:
Tejun Heo <htejun@gmail.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by:
Jeff Garzik <jeff@garzik.org>
-
Tejun Heo authored
ICH6 R/Ms share PCI ID between piix and ahci modes and we've been allowing ahci to attach regardless of how BIOS configured it. However, enabling AHCI mode when the controller is in combined mode can result in unexpected behavior. Don't attach if the controller is in combined mode. Signed-off-by:
-
Peter Schwenke authored
Add Toshiba Tecra M4 to broken suspend list. This is from OSDL bugzilla bug 7780. Signed-off-by:
Peter Schwenke <peter@bluetoad.com.au> Signed-off-by:
-
Tejun Heo authored
There isn't much point in reporting -EOPNOTSUPP as failure. Also the message was missing newline. Signed-off-by:
-
Sreenivasa Honnur authored
- Making sure register initialisation is complete before proceeding further. The driver must wait until initialization is complete before attempting to access any other device registers. Signed-off-by:
Surjit Reang <surjit.reang@neterion.com> Signed-off-by:
Sreenivasa Honnur <sreenivasa.honnur@neterion.com> Signed-off-by:
-
Benjamin Herrenschmidt authored
This updates the copyright notices of the new EMAC driver to avoid confusion as who is to be blamed for new bugs. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
-
