1. 29 Sep, 2014 1 commit
    • Rodrigo Vivi's avatar
      drm/i915: Minimize the huge amount of unecessary fbc sw cache clean. · 1d73c2a8
      Rodrigo Vivi authored
      The sw cache clean on BDW is a tempoorary workaround because we cannot
      set cache clean on blt ring with risk of hungs. So we are doing the cache clean on sw.
      However we are doing much more than needed. Not only when using blt ring.
      So, with this extra w/a we minimize the ammount of cache cleans and call it only
      on same cases that it was being called on gen7.
      
      The traditional FBC Cache clean happens over LRI on BLT ring when there is a
      frontbuffer touch happening. frontbuffer tracking set fbc_dirty variable
      to let BLT flush that it must clean FBC cache.
      
      fbc.need_sw_cache_clean works in the opposite information direction
      of ring->fbc_dirty telling software on frontbuffer tracking to perform
      the cache clean on sw side.
      
      v2: Clean it a little bit and fully check for Broadwell instead of gen8.
      
      v3: Rebase after frontbuffer organization.
      
      v4: Wiggle confused me. So fixing v3!
      
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      1d73c2a8
  2. 24 Sep, 2014 3 commits
  3. 23 Sep, 2014 2 commits
  4. 19 Sep, 2014 34 commits