- 18 Oct, 2018 14 commits
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Stephen Boyd authored
Merge branches 'clk-actions-reset', 'clk-imx7-init-critical', 'clk-mmp2-ids' and 'clk-at91-pmc-rework' into clk-next - Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs - Rework at91 PMC clock driver for new DT bindings * clk-actions-reset: clk: actions: Add Actions Semi S900 SoC Reset Management Unit support clk: actions: Add Actions Semi S700 SoC Reset Management Unit support clk: actions: Add Actions Semi Owl SoCs Reset Management Unit support dt-bindings: reset: Add binding constants for Actions Semi S900 RMU dt-bindings: reset: Add binding constants for Actions Semi S700 RMU dt-bindings: clock: Add reset controller bindings for Actions Semi Owl SoCs clk: actions: Cache regmap info in private clock descriptor * clk-imx7-init-critical: clk: imx7d: remove CLK_IS_CRITICAL flag for arm_a7_root_clk clk: imx: cpu clock should be always critical clk: imx: imx7d: remove clks_init_on array clk: imx: imx7d: remove unnecessary clocks from clks_init_on array * clk-mmp2-ids: clk: mmp2: fix the clock id for sdh2_clk and sdh3_clk * clk-at91-pmc-rework: clk: at91: move DT compatibility code to its own file clk: at91: add at91sam9rl PMC driver clk: at91: add at91sam9x5 PMCs driver clk: at91: add at91sam9260 PMC driver clk: at91: add sama5d2 PMC driver clk: at91: add sama5d4 pmc driver clk: at91: add new DT lookup function dt-bindings: clk: at91: Document new PMC binding clk: at91: add pmc_data struct and helpers clk: at91: allow clock registration from C code clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated() clk: at91: audio-pll: separate registration from DT parsing clk: at91: h32mx: separate registration from DT parsing clk: at91: generated: SSCs don't have a gclk clk: at91: audio-pll: fix audio pmc type
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Stephen Boyd authored
- Nvidia Tegra clk driver MBIST workaround fix - clk_bulk_get_all() API and friends to get all the clks for a device * clk-tegra: clk: tegra210: Include size.h for compilation ease clk: tegra: Fixes for MBIST work around clk: tegra: probe deferral error reporting * clk-bulk-get-all: clk: add managed version of clk_bulk_get_all clk: add new APIs to operate on all available clocks clk: bulk: add of_clk_bulk_get()
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Stephen Boyd authored
- Ingenic jz4725b CGU * clk-ingenic-jz4725b: clk: Add Ingenic jz4725b CGU driver dt-bindings: clock: Add jz4725b-cgu.h header dt-bindings: clock: ingenic: Explicitly list compatible strings clk: ingenic: Add proper Kconfig entries
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Stephen Boyd authored
- Qualcomm QCS404 GCC support * clk-qcom-qcs404: clk: qcom: gcc: Add global clock controller driver for QCS404 clk: qcom: Export clk_alpha_pll_configure()
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Stephen Boyd authored
- Qualcomm SDM660 GCC support * clk-qcom-sdm660: clk: qcom: gcc-sdm660: Add MODULE_LICENSE clk: qcom: Add Global Clock controller (GCC) driver for SDM660
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Stephen Boyd authored
- Hisilicon 3670 SoC support * clk-samsung: dt-bindings: clock: samsung: Add SPDX license identifiers clk: samsung: Use clk_hw API for calling clk framework from clk notifiers clk: samsung: exynos5420: Enable PERIS clocks for suspend clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420 clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend clk: samsung: Remove obsolete code for Exynos4412 ISP clocks clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume clk: samsung: exynos5420: Use generic helper for handling suspend/resume clk: samsung: exynos4: Use generic helper for handling suspend/resume clk: samsung: Add support for setting registers state before suspend clk: samsung: exynos5250: Use generic helper for handling suspend/resume clk: samsung: s5pv210: Use generic helper for handling suspend/resume clk: samsung: s3c64xx: Use generic helper for handling suspend/resume clk: samsung: s3c2443: Use generic helper for handling suspend/resume clk: samsung: s3c2412: Use generic helper for handling suspend/resume clk: samsung: s3c2410: Use generic helper for handling suspend/resume clk: samsung: Remove excessive include * clk-hisi3670: clk: hisilicon: Add clock driver for Hi3670 SoC dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk * clk-at91-div-0: clk: at91: Fix division by zero in PLL recalc_rate()
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Stephen Boyd authored
* clk-ti: clk: ti: Prepare for remove of OF node name clk: Clean up suspend/resume coding style clk: ti: Add functions to save/restore clk context clk: clk: Add clk_gate_restore_context function clk: Add functions to save/restore clock context en-masse clk: ti: dra7: add new clkctrl data clk: ti: dra7xx: rename existing clkctrl data as compat data clk: ti: am43xx: add new clkctrl data for am43xx clk: ti: am43xx: rename existing clkctrl data as compat data clk: ti: am33xx: add new clkctrl data for am33xx clk: ti: am33xx: rename existing clkctrl data as compat data clk: ti: clkctrl: replace dashes from clkdm name with underscore clk: ti: clkctrl: support multiple clkctrl nodes under a cm node dt-bindings: clock: dra7xx: add clkctrl indices for new data layout dt-bindings: clock: am43xx: add clkctrl indices for new data layout dt-bindings: clock: am33xx: add clkctrl indices for new data layout
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Stephen Boyd authored
- TI SCI clks on K3 SoCs * clk-k3-tisci: clk: keystone: add missing MODULE_LICENSE clk: keystone: Enable TISCI clocks if K3_ARCH
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Stephen Boyd authored
Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', 'clk-mvebu-dup' and 'clk-davinci' into clk-next - S2RAM support for Marvell mvebu periph clks * clk-mvebu-periph-pm: clk: mvebu: armada-37xx-periph: add suspend/resume support clk: mvebu: armada-37xx-periph: save the IP base address in the driver data * clk-meson: clk: meson: meson8b: use the regmap in the internal reset controller clk: meson: meson8b: register the clock controller early clk: meson-axg: pcie: drop the mpll3 clock parent clk: meson: axg: round audio system master clocks down clk: meson: clk-pll: drop hard-coded rates from pll tables clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: add enable bit * clk-allwinner: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position * clk-mvebu-dup: clk: mvebu: ap806: Remove superfluous of_clk_add_provider * clk-davinci: clk: davinci: kill davinci_clk_reset_assert/deassert()
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Stephen Boyd authored
- Qualcomm SDM845 camera clock controller * clk-qcom-sdm845-camcc: clk: qcom: Add camera clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Camera clock bindings * clk-mtk-unused: clk: mediatek: remove unused array audio_parents
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Stephen Boyd authored
* clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
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Stephen Boyd authored
- Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds * clk-dt-name: clk: Convert to using %pOFn instead of device_node.name * clk-ti-of-node: clk: ti: fix OF child-node lookup * clk-sa: clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe reset: hisilicon: fix potential NULL pointer dereference clk: cdce925: release child device nodes clk: qcom: clk-branch: Use true and false for boolean values
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Stephen Boyd authored
Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include', 'clk-qcom-8996-missing' and 'clk-qcom-qspi' into clk-next - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 * clk-spdx: clk: mvebu: use SPDX-License-Identifier clk: renesas: Convert to SPDX identifiers clk: renesas: use SPDX identifier for Renesas drivers clk: s2mps11,s3c64xx: Add SPDX license identifiers clk: max77686: Add SPDX license identifiers * clk-qcom-dfs: clk: qcom: Allocate space for NULL terimation in DFS table clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845 clk: qcom: Add support for RCG to register for DFS * clk-smp2s11-include: clk: s2mps11: Use existing defines from bindings for clock IDs * clk-qcom-8996-missing: clk: qcom: Add some missing gcc clks for msm8996 * clk-qcom-qspi: clk: qcom: Add qspi (Quad SPI) clocks for sdm845 clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
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Stephen Boyd authored
Add a module license to match the license at the top of this file and silence a build warning. Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 17 Oct, 2018 18 commits
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Alexandre Belloni authored
Move all the DT backward compatibility code to its own file so it can be deleted later. Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
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Alexandre Belloni authored
Add a driver for the PMC clocks of the at91sam9rl SoC. Signed-off-by:
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Alexandre Belloni authored
Add a driver for the PMC clocks of the at91sam9x5 SoCs Signed-off-by:
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Alexandre Belloni authored
Add a driver for the PMC clocks of the at91sam9260, at91sam9261, at91am9263 and at91sam9g20 SoCs. Signed-off-by:
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Alexandre Belloni authored
Add a driver for the PMC clocks of the sama5d2 Signed-off-by:
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Alexandre Belloni authored
Add a driver for the PMC clocks of the sama5d4 Signed-off-by:
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Alexandre Belloni authored
Add a new DT lookup function to lookup for PMC clocks. Note that the #ifndef AT91_PMC_MOSCS section will be removed once all the platforms are converted. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Alexandre Belloni authored
Document the new PMC binding with only one PMC node for all the PMC clocks instead of one node per clock as this proved to be problematic. Reviewed-by:
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Alexandre Belloni authored
Add a new strut to handle references to all the PMC clocks and implement allocation/free helpers. Signed-off-by:
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Alexandre Belloni authored
Remove static keyword to allow functions to be used from other units. Also move some struct and function declarations to pmc.h Signed-off-by:
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Alexandre Belloni authored
Set gck->audio_pll_allowed in at91_clk_register_generated. This makes it easier to do it from code that is not parsing device tree. Also, this fixes an issue where the resulting clk_hw can be dereferenced before being tested for error. Fixes: 1a1a36d7 ("clk: at91: clk-generated: make gclk determine audio_pll rate") Signed-off-by:
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Alexandre Belloni authored
Separate registration out of of_sama5d2_clk_audio_pll*_setup to allow other code to use it. Signed-off-by:
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Alexandre Belloni authored
Separate registration out of of_sama5d4_clk_h32mx_setup to allow other code to use it. Signed-off-by:
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Alexandre Belloni authored
As the SSCs don't have gclk, don't check for their ID to allow them to set the audio pll rate. Signed-off-by:
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Alexandre Belloni authored
The allocation for the audio pmc is using the size of struct clk_audio_pad instead of struct clk_audio_pmc. This works fine because the former is larger than the latter but it is safer to be correct. Fixes: ("0865805d clk: at91: add audio pll clock drivers") Signed-off-by: -
Lubomir Rintel authored
A typo that makes it impossible to get the correct clocks for MMP2_CLK_SDH2 and MMP2_CLK_SDH3. Signed-off-by:
Lubomir Rintel <lkundrak@v3.sk> Fixes: 1ec770d9 ("clk: mmp: add mmp2 DT support for clock driver") Signed-off-by:
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Anson Huang authored
i.MX7D uses virtual cpu clock of "arm" clock to be child clock of "arm_a7_root_clk" and it is with CLK_IS_CRITICAL flag set, so no need to add CLK_IS_CRITICAL flag for keeping "arm_a7_root_clk" use count correct, latest clock tree is as below in clk_summary: pll_arm_main 1 1 0 792000000 0 pll_arm_main_bypass 1 1 0 792000000 0 pll_arm_main_clk 1 1 0 792000000 0 arm_a7_src 1 1 0 792000000 0 arm_a7_cg 1 1 0 792000000 0 arm_a7_div 1 1 0 792000000 0 arm_a7_root_clk 1 1 0 792000000 0 arm 1 1 0 792000000 Signed-off-by:Anson Huang <Anson.Huang@nxp.com> Signed-off-by:
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Anson Huang authored
Add CLK_IS_CRITICAL flag for cpu clock type to make cpu clock use count correct, as cpu clock should be always critical. Signed-off-by:
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- 16 Oct, 2018 8 commits
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Gregory CLEMENT authored
The parent clock is get only to have its name, and then the clock is no more used, so we can safely free it using clk_put. Furthermore as between the successful devm_clk_get() and the devm_clk_put() call we don't exit the probe function in error so I can use non managed version of clk_get() and clk_put(). Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by:
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Dong Aisheng authored
This patch introduces the managed version of clk_bulk_get_all. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Tested-by:
Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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Dong Aisheng authored
This patch introduces of_clk_bulk_get_all and clk_bulk_x_all APIs to users who just want to handle all available clocks from device tree without need to know the detailed clock information likes clock numbers and names. This is useful in writing some generic drivers to handle clock part. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by:
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Dong Aisheng authored
'clock-names' property is optional in DT, so of_clk_bulk_get() is introduced here to handle this for DT users without 'clock-names' specified. Later clk_bulk_get_all() will be implemented on top of it and this API will be kept private until someone proves they need it because they don't have a struct device pointer. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Russell King <linux@arm.linux.org.uk> Reported-by:
Shawn Guo <shawnguo@kernel.org> Tested-by:
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Stephen Boyd authored
You can't compile this file by itself because it uses SZ_64K from sizes.h but doesn't include it. Instead it relies on some certain configuration pulling that in implicitly somewhere else. Just add the include to make random compile testing easier. Signed-off-by: -
Joseph Lo authored
Fix some incorrect data in LVL2 offset and bit mask. Fixes: e403d005 ("clk: tegra: MBIST work around for Tegra210") Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
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Marcel Ziswiler authored
Actually report the error code from devm_regulator_get() which may as well just be a probe deferral. Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Anson Huang authored
Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by:
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