- 30 Jun, 2016 6 commits
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Stephen Boyd authored
* clk-st-critical: clk: st: clkgen-pll: Detect critical clocks clk: st: clkgen-fsyn: Detect critical clocks clk: st: clk-flexgen: Detect critical clocks
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Lee Jones authored
Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. Clocks are marked as CRITICAL using clk flags. This patch also ensures flags are peculated through the framework in the correct manner. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Lee Jones authored
Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. Clocks are marked as CRITICAL using clk flags. This patch also ensures flags are peculated through the framework in the correct manner. Signed-off-by:
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Lee Jones authored
Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. While we're at it, reduce the coverage of the flex_flags variable, since it's only really used in a single for() loop. Signed-off-by:
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Stephen Boyd authored
* clk-hi6220-rtc: clk: hi6220: Add RTC clock for pl031
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Zhangfei Gao authored
Adds clk support for the pl031 RTC on hi6220 Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Guodong Xu <guodong.xu@linaro.org> Signed-off-by:
Zhangfei Gao <zhangfei.gao@linaro.org> [jstultz: Forward ported, tweaked commit description] Signed-off-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
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- 29 Jun, 2016 3 commits
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Stephen Boyd authored
* clk-notify: clk: Provide notifier stubs when !COMMON_CLK
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull second batch of Renesas clk driver updates from Geert Uytterhoeven: - Add support for R-Car V2H, - Add FDP1, DRIF, and thermal clocks on R-Car H3, - Correct a wrong parent clock. * tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7795: Add THS/TSC clock clk: renesas: r8a7795: Add DRIF clock clk: renesas: r8a7795: Correct lvds clock parent clk: renesas: r8a7795: Provide FDP1 clocks clk: renesas: Add R8A7792 support clk: renesas: mstp: Document R8A7792 support clk: renesas: rcar-gen2: Document R8A7792 support
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Krzysztof Kozlowski authored
The clk notifier symbols are hidden by COMMON_CLK. However on some platforms HAVE_CLK might be set while COMMON_CLK not which leads to compile test build errors like: $ make.cross ARCH=sh drivers/devfreq/tegra-devfreq.c: In function 'tegra_actmon_rate_notify_cb': >> drivers/devfreq/tegra-devfreq.c:391:16: error: 'POST_RATE_CHANGE' undeclared (first use in this function) if (action != POST_RATE_CHANGE) ^ drivers/devfreq/tegra-devfreq.c: In function 'tegra_devfreq_probe': >> drivers/devfreq/tegra-devfreq.c:654:8: error: implicit declaration of function 'clk_notifier_register' [-Werror=implicit-function-declaration] err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb); ^ Export the macros and data type declarations outside of COMMON_CLK ifdef and provide stubs to fix the compile testing. Reported-by:kbuild test robot <lkp@intel.com> Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by:
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by:
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- 28 Jun, 2016 2 commits
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull support for Renesas R-car M3-W from Geert Uytterhoeven: Add initial support for the Clock Pulse Generator and Module Standby and Software Reset modules on the Renesas R-Car M3-W SoC: - Basic core clocks, - SCIF2 (console) module clock, - INTC-AP (GIC) module clock. * tag 'clk-renesas-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Add support for R-Car M3-W clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code clk: renesas: Add r8a7796 CPG Core Clock Definitions clk: renesas: cpg-mssr: Document r8a7796 support
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Stephen Boyd authored
This clk is critical to operation of the SoC and should never be turned off. Furthermore, there are no consumers of this clk so let's just delete it so things like eMMC work. Reported-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0 ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by:
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- 23 Jun, 2016 15 commits
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Michael Turquette authored
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Michael Turquette authored
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
Michael Turquette <mturquette@baylibre.com>
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Michael Turquette authored
Add documentations for the clock controller. Tested-by:
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Michael Turquette authored
Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add in a couple of new bitfields for further dividing the clock rate to achieve rates with fractional hertz. Tested-by:
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Michael Turquette authored
MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and GXBB they appear to be only derived from fixed_pll. Add support for these clock types so that they can be added to their respective drivers. Tested-by:
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Michael Turquette authored
There are a series of peripheral and system gate clocks that fan out from the clk81 signal. Add a helper macro to statically initialize these gate clocks. Tested-by:
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Michael Turquette authored
Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by:
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Michael Turquette authored
This patch creates a proper platform_driver for the meson8b clock controller. Use of CLK_OF_DECLARE is removed, and can be added back in later if very early registration of some clocks is required. Tested-by:
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Michael Turquette authored
Remove the composite clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. To preserve git bisect this patch also flips the switch and starts using of_clk_add_hw_provider instead of the deprecated meson_clk_register_clks method. As a byproduct clk.c can be deleted. Tested-by:
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Michael Turquette authored
This clock is undocumented and always orphaned. Get rid of it until we have more complete clock tree documentation. Tested-by:
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Michael Turquette authored
Remove the cpu clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Ninja rename a5_clk to cpu_clk to better align with cpufreq convention. Tested-by:
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Michael Turquette authored
Remove the fixed factor registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Tested-by:
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Michael Turquette authored
Remove the pll registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Tested-by:
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Michael Turquette authored
Remove the fixed_rate registration function and helpers from clkc.[ch]. Replace unnecessary configuration struct with static initialization of the desired clock type. While we're here, begin the transition to a proper platform_driver and call of_clk_add_hw_provider with a shiny new struct clk_hw_onecell_data. Tested-by:
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Michael Turquette authored
The register offsets in the data sheet are confusing. Document them more thoroughly. Tested-by:
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- 21 Jun, 2016 14 commits
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Khiem Nguyen authored
Signed-off-by:
Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Ramesh Shanmugasundaram authored
This patch adds DRIF module clocks for r8a7795 SoC. Signed-off-by:
Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by:
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Geert Uytterhoeven authored
According to the latest information, the parent clock of the LVDS module clock is the S0D4 clock, not the S2D1 clock. Note that this change has no influence on actual operation, as the rcar-du LVDS encoder driver doesn't use the parent clock's rate. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Kieran Bingham authored
Reviewed-by:
Kieran Bingham <kieran@bingham.xyz> Signed-off-by:
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Sergei Shtylyov authored
Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Renesas R8A7792 SoC also has the CPG MSTP clocks... Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Sergei Shtylyov authored
Renesas R8A7792 SoC is a member of the R-Car gen2 family and so has CPG... Signed-off-by:
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git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Merge changes from Sylwester Nawrocki for samsung clk drivers: - a fix for exynos7 to prevent gating some critical CMU clocks, - addition of CPU clocks for CPU frequency scaling on Exynos5433 SoCs, - additions for exynos5410 SoC required for Odroid XU board support, - register accessors fixes for kernels built for big endian operation (mostly exynos4 SoCs), - Exynos5433 clock definitions fixes required for suspend to RAM and the audio subsystem operation, - many cleanups changing attributes of the clock initializer data * tag 'clk-samsung-4.8' of git://linuxtv.org/snawrocki/samsung: (41 commits) clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flags to avoid hang during S2R clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD UART clk: samsung: exynos4: fixup reg access on be clk: samsung: fixup endian in pll clk clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks clk: samsung: exynos5433: add CPU clocks configuration data and instantiate CPU clocks clk: samsung: cpu: prepare for adding Exynos5433 CPU clocks clk: samsung: exynos5433: prepare for adding CPU clocks clk: samsung: Suppress unbinding to prevent theoretical attacks clk: samsung: exynos5420: Set ID for aclk333 gate clock clk: samsung: exynos5410: Add TMU clock clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks clk: samsung: exynos5410: Add serial3, USB and PWM clocks clk: samsung: exynos3250: Move PLL rates data to init section clk: samsung: Fully constify mux parent names clk: samsung: exynos5250: Move sleep init function to init section clk: samsung: exynos5420: Move sleep init function and PLL data to init section clk: samsung: exynos5433: Move PLL rates data to init section clk: samsung: exynos5433: Constify all clock initializers ...
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Peng Fan authored
Correct comments for __clk_determine_rate. Signed-off-by:
Peng Fan <van.freenix@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Roman Volkov authored
PLL clock on WM8650 is calculated in the following way: M * parent [O1] => / P [O2] => / D [O3] Where O2 is 600MHz >= (M * parent) / P >= 300MHz. Current algorithm does not met this requirement, so that the function may return rates which are not supported by the hardware. This patch fixes the algorithm and simplifies the code, reducing the calculation time by ~10000 times (according to usermode app) by removing the nested loops. Signed-off-by:
Roman Volkov <rvolkov@v1ros.org> Signed-off-by:
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Arnd Bergmann authored
This fixes some false positive warnings we get with older compiler versions: clk-vt8500.c: In function ‘wm8650_find_pll_bits’: clk-vt8500.c:430:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:429:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:428:14: ‘best_mul’ may be used uninitialized in this function clk-vt8500.c: In function ‘wm8750_find_pll_bits’: clk-vt8500.c:509:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:508:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:507:14: ‘best_mul’ may be used uninitialized in this function clk-vt8500.c: In function ‘wm8850_find_pll_bits’: clk-vt8500.c:560:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:559:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:558:14: ‘best_mul’ may be used uninitialized in this function As the local variables are only use for temporaries, we can just as well assign the final values directly, which also makes the code slightly shorter. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Lee Jones authored
Signed-off-by:
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Ben Dooks authored
Fix the warning from missing "clk.h" include which defines hi6220_register_clkdiv() function. drivers/clk/hisilicon/clkdivider-hi6220.c:102:12: warning: symbol 'hi6220_register_clkdiv' was not declared. Should it be static? Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by:
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Ben Dooks authored
Fix the implicit declaration of iproc_armpll_setup() by including clk-iproc.h which defines it. Fixes the warning: drivers/clk/bcm/clk-iproc-armpll.c:242:13: warning: symbol 'iproc_armpll_setup' was not declared. Should it be static? Signed-off-by:
Ray Jui <ray.jui@broadcom.com> Signed-off-by:
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