- 27 Sep, 2018 40 commits
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James Zhu authored
Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers can't be directly accessed under DPG(Dynamic Power Gate) mode. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Christian König authored
Everything that isn't related to the IH ring. Signed-off-by:
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Christian König authored
Add a callback to amdgpu_ih_process to remove most of the IV logic. Signed-off-by:
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Andrey Grodzovsky authored
Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_process to let amdgpu_fence_fallback know fences were actually processed and then print the warning. v3: Always return true if seq != last_seq Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Christian König authored
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. Signed-off-by:
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Christian König authored
We always want those to be setup correctly. Signed-off-by:
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Christian König authored
That is superflous here. Signed-off-by:
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Huang Rui authored
While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by:
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Rex Zhu authored
Need to disable dpm features before halt rlc. Acked-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
the CG related registers have been programed in golden setting PG register default value is 0. Acked-by:
Hang Zhou <hang.zhou@amd.com> Signed-off-by:
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Rex Zhu authored
before halt rlc/cp, need to 1. enter rlc safe mode 2. wait rlc/cp idle Acked-by:
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Rex Zhu authored
change function name gfx_v6/7/8/9_0_gpu_init to gfx_v6/7/8/9_0_constants_init. this function is just for init gfx constants such as max pipes, render backends... Reviewed-by:
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Andrey Grodzovsky authored
Deactivate SW interrupt fallback when all emited fences are completed. Also switch interrupt SW fallback message from INFO to WARN. v2: shorten the warning message a bit and only re-activate the timer during processing if it was already activated before. (Christian) Signed-off-by:
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Shaoyun Liu authored
Add Vega20 device IDs, device info and enable it in KFD. Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Shaoyun Liu authored
Add Vega20 support in amdgpu_amdkfd_device_probe. Signed-off-by:
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Shaoyun Liu authored
amdgpu_gpuvm_get_process_page_dir should return the page table address in the format expected by the pm4_map_process packet for all ASIC generations. Signed-off-by:
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Shaoyun Liu authored
Vega20 supports 8 SDMA queues per engine Signed-off-by:
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Emily Deng authored
Correct the format For vega10 sriov, the sdma doorbell must be fixed as follow to keep the same setting with host driver, or it will happen conflicts. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Acked-by:
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Shaoyun Liu authored
Change doorbell assignments to allow routing doorbells for 8 user mode SDMA queues per engine. Signed-off-by:
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Felix Kuehling authored
struct vi_sdma_mqd is defined in vi_structs.h. Signed-off-by:
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Jay Cornwall authored
Wavefront context save data is of interest to userspace clients for debugging static wavefront state. The MQD contains two parameters required to parse the control stack and the control stack itself is kept in the MQD from gfx9 onwards. Add an ioctl to fetch the context save area and control stack offsets and to copy the control stack to a userspace address if it is kept in the MQD. Signed-off-by:
Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by:
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Felix Kuehling authored
Also save the version in struct kfd_dev so we only need to query it once. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
This enables KFD_EVENT_TYPE_HW_EXCEPTION notifications to user mode in response to bad opcodes in a CP queue. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Emily Deng authored
KFD module doesn't support TONGA SRIOV, if init KFD module in TONGA SRIOV environment, it will let compute ring IB test fail. Signed-off-by:
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Eric Huang authored
Add the flags of properties according to Asic type and pcie capabilities. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Signed-off-by:
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Andrey Grodzovsky authored
This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55. This commit breaks KCQ IB test and S3 on Polaris 11. Signed-off-by:
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James Zhu authored
When VCN PG state is unchanged, it is unnecessary to reset power gate state Signed-off-by:
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zhong jiang authored
kfree has taken the null pointer into account. hence it is safe to remove the redundant null pointer check before kfree. Signed-off-by:
zhong jiang <zhongjiang@huawei.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
Print the enabled smc feature mask in amdgpu_pm_info for debugging. Reviewed-by:
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Alex Deucher authored
So we can query what features are enabled for debugging. Reviewed-by:
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Alex Deucher authored
So we can query what features are enabled for debugging. Reviewed-by:
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Alex Deucher authored
So we can query what features are enabled for debugging. Reviewed-by:
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Alex Deucher authored
For getting the 64 bit enabled smc feature mask from vega parts. Reviewed-by:
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Alex Deucher authored
For consistency with other asics. Reviewed-by:
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Alex Deucher authored
For consistency with other asics. Reviewed-by:
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Alex Deucher authored
to vega10_smumgr.c. For consistency with other vega parts. Reviewed-by:
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Alex Deucher authored
For consistency with other vega parts. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] The DISPCLK value was previously requested to be 15% higher for all ASICs that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and the dce110 set bandwidth codepath this was removed for power saving considerations. That change caused display corruption under certain hardware configurations with Vega10. [How] The 15% DISPCLK increase is brought back but only on dce110 for now. This is should be a temporary workaround until the root cause is sorted out for why this occurs on Vega (or other ASICs, if reported). Tested-by:
Nick Sarnie <sarnex@gentoo.org> Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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SivapiriyanKumarasamy authored
[WHY] Previously night light forced a full update by applying a transfer function update regardless of if it was changed. This logic was removed, Now gamma surface updates are only applied when there is also a plane info update, this does not work in cases such as using the night light slider. [HOW] When moving the night light slider we will perform a full update if the gamma has changed and there is a surface, even when the surface has not changed. Also get stream updates in setgamma prior to update planes and stream. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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