- 15 May, 2018 40 commits
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Alex Deucher authored
DC is preferred. Signed-off-by:Alex Deucher <alexander.deucher@amd.com>
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Jerry (Fangzhi) Zuo authored
Add CHIP_VEGAM Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
Implement device IDs for VEGAM Signed-off-by:
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Leo Liu authored
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Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
v2: use proper register rather than hardcoding. Signed-off-by:
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Leo Liu authored
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Leo Liu authored
Directly loaded by VBIOS Signed-off-by:
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Mathieu Malaterre authored
AGP mode is unstable on PowerPC. Symptoms are generally of the form: [ 1228.795711] radeon 0000:00:10.0: ring 0 stalled for more than 10240msec Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Mathieu Malaterre <malat@debian.org> Signed-off-by:
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Rex Zhu authored
when bit14 in module parameter ppfeaturemask was set. od feature will be enabled on Vega10 except vbios not support. user can read od range by reading sysfs pp_od_clk_voltage, cat pp_od_clk_voltage OD_SCLK: 0: 852Mhz 800mV 1: 991Mhz 900mV 2: 1138Mhz 950mV 3: 1269Mhz 1000mV 4: 1348Mhz 1050mV 5: 1399Mhz 1100mV 6: 1440Mhz 1150mV 7: 1500Mhz 1200mV OD_MCLK: 0: 167Mhz 800mV 1: 500Mhz 800mV 2: 800Mhz 950mV 3: 945Mhz 1000mV OD_RANGE: SCLK: 852MHz 2200MHz MCLK: 167MHz 1500MHz VDDC: 800mV 1200mV and can configure the clock/voltage by writing pp_od_clk_voltage for example: echo "s 0 900 820">pp_od_clk_voltage to change the sclk/vddc to 900MHz and 820 mV in dpm level0. echo "r" to change the clk/voltage to default value. echo "c">pp_od_clk_voltage to commit the change v2: squash in warning fix (Alex) Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Luc Van Oostenryck authored
The method struct drm_connector_helper_funcs::mode_valid is defined as returning an 'enum drm_mode_status' but the driver implementation for this method uses an 'int' for it. Fix this by using 'enum drm_mode_status' in the driver too. Reviewed-by:
Luc Van Oostenryck <luc.vanoostenryck@gmail.com> Signed-off-by:
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Luc Van Oostenryck authored
The method struct drm_connector_helper_funcs::mode_valid is defined as returning an 'enum drm_mode_status' but the driver implementation for this method uses an 'int' for it. Fix this by using 'enum drm_mode_status' in the driver too. Signed-off-by:
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Luc Van Oostenryck authored
The method struct vga_switcheroo_handler::get_client_id() is defined as returning an 'enum vga_switcheroo_client_id' but the implementation in this driver, radeon_atpx_get_client_id(), returns an 'int'. Fix this by returning 'enum vga_switcheroo_client_id' in this driver too. Signed-off-by:
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Luc Van Oostenryck authored
The method struct vga_switcheroo_handler::get_client_id() is defined as returning an 'enum vga_switcheroo_client_id' but the implementation in this driver, amdgpu_atpx_get_client_id(), returns an 'int'. Fix this by returning 'enum vga_switcheroo_client_id' in this driver too. Signed-off-by:
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welu authored
1. support more than 8 values when setting get_pp_dpm_mclk/ sclk/pcie, the former design just parse command format like "echo xxxx > pp_dpm_sclk" and current can parse "echo xx xxx xxxx > pp_dpm_sclk" whose operation is more user-friendly and convinent and can offer more values; 2. be compatible with former design like "xx". 3. add DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie Bug:KFD-385 Signed-off-by:
welu <wei.lu2@amd.com> Reviewed-by:
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Nicolai Hähnle authored
Otherwise, the SQ may skip some of the register writes, or shader waves may be allocated where we don't expect them, so that as a result we don't actually reset all of the register SRAMs. This can lead to spurious ECC errors later on if a shader uses an uninitialized register. Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
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Junwei Zhang authored
Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
David Zhou <david1.zhou@amd.com> Signed-off-by:
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Samuel Li authored
Enables sg display if vram size <= THRESHOLD(256M); otherwise still use vram as display buffer. This patch fixed some potention issues introduced by change "allow framebuffer in GART memory as well" due to CZ/ST hardware limitation. v2: Change default setting to auto. v3: Move some logic from amdgpu_display_framebuffer_domains() to pin function, suggested by Christian. v4: Split into several patches. v5: Drop module parameter for now. Signed-off-by:Samuel Li <Samuel.Li@amd.com> Reviewed-by:
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Alex Deucher authored
Set query to the power value so we actually return it. Fixes no power value returned on asics with the new query. Tested-by:
Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by:
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Rex Zhu authored
when user cat pp_od_clk_voltage add display info about the sclk/mclk/vddc range that user can overdrive output as: OD_SCLK: 0: 300MHz 900mV 1: 400MHz 912mV 2: 500MHz 925mV 3: 600MHz 937mV 4: 700MHz 950mV 5: 800MHz 975mV 6: 900MHz 987mV 7: 1000MHz 1000mV OD_MCLK: 0: 300MHz 900mV 1: 1500MHz 912mV OD_RANGE: SCLK: 300MHz 1200MHz MCLK: 300MHz 1500MHz VDDC: 700mV 1200mV also 1. remove unnecessary whitespace before a quoted newline 2. change unit of frequency Mhz to MHz Reviewed-by:
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Rex Zhu authored
read vddc range from vbios. Reviewed-by:
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Rex Zhu authored
if vddc restore to default value, driver clear the bit of DPMTABLE_OD_UPDATE_VDDC and need to repopulate sclk and mclk table. 1. Remove variable i checking code. 2. move clear DPMTABLE_OD_UPDATE_VDDC bit to the end of the function to avoid sclk table will not be updated. Reviewed-by:
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Rex Zhu authored
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Evan Quan <evan.quan@amd.com> Signed-off-by:
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Rex Zhu authored
to keep consistent with other asics Reviewed-by:
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