- 11 Jun, 2013 9 commits
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Sergei Shtylyov authored
Since we're now going to setup the USBPCTRL0 register using the USB PHY device's platform data, we now need a way to pass those platform data from the board file to the device which is situated in setup-r8a7779.c -- and what I'm suggesting is r8a7779_add_usb_phy_device() that will register USB PHY platform device with the passed platform data using platform_device_register_resndata() call; creating this function involves deletion of 'usb_phy_device' from r8a7779_devices_dt[], so that it will no longer be registered for the generic R8A7779 machine (where we can't provide the platform data anyway), hence EHCI/OHCI drivers will fail to load as well. For the Marzen board, this new function will be called from marzen_init() to register the USB PHY device early enough. Note that the board and the SoC code have to be in one patch to keep the code bisectable... The patch has been tested on the Marzen board. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [horms+renesas@verge.net.au: manually applied] Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
Currently the driver hard-codes USBPCTRL0 register to 0. It is wrong since this register contains board-specific USB ports configuration and so its value should be somehow passed via the platform data. Add the global header file containing 'struct rcar_phy_platform_data' consisting of the various bit fields describing USB ports' pin configuration. Signed-off-by:
Felipe Balbi <balbi@ti.com> Signed-off-by:
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Sergei Shtylyov authored
The memory region that is used by the driver overlaps EHCI and OHCI register regions for absolutely no reason now -- fix it by adding offset of 0x800 to the base address, changing the register #define's accordingly. This has extra positive effect that we now can use devm_ioremap_resource()... Note that the driver and the SoC code have to be in one patch to keep the code bisectable... The patch has been tested on the Marzen board. Signed-off-by:
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Sergei Shtylyov authored
Now that 'drivers/usb/phy/phy-rcar-usb.c' doesn't require the second memory resource anymore, we can remove it from the R8A7779's USB PHY platform device. Signed-off-by:
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Sergei Shtylyov authored
Now that the EHCI internal buffer setup is done by the platform code, we can remove such code from this driver as it never really belonged here. We also no longer need the 2nd memory region now (2nd EHCI controller is simply missing in e.g. R8A7778 SoC). The patch has been tested on the Marzen and BOCK-W boards. Signed-off-by:
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Sergei Shtylyov authored
Setup the EHCI internal buffer (before EHCI driver has a chance to touch the registers) using the pre_setup() method in 'struct usb_ehci_pdata'. The patch has been tested on the Marzen board. Signed-off-by:
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Sergei Shtylyov authored
Sometimes there is a need to initialize some non-standard registers mapped to the EHCI region before accessing the standard EHCI registers. Add pre_setup() method with 'struct usb_hcd *' parameter to be called just before ehci_setup() to the 'ehci-platform' driver's platform data for this purpose... While at it, add the missing incomplete declaration of 'struct platform_device' to <linux/usb/ehci_pdriver.h>... The patch has been tested on the Marzen and BOCK-W boards. Suggested-by:
Alan Stern <stern@rowland.harvard.edu> Signed-off-by:
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Sergei Shtylyov authored
USB EHCI, OHCI, and common PHY are the SoC devices but are wrongly defined and registered in the Marzen board file. Move the data and code to their proper place in setup-r8a7779.c; while at it, we have to rename r8a7779_late_devices[] to r8a7779_standard_devices[] -- this seems legitimate since they are registered from r8a7779_add_standard_devices() anyway. Note that I'm deliberately changing the USB PHY platform device's 'id' field from (previously just omitted) 0 to -1 as the device is a single of its kind. Note also that the board and SoC code have to be in one patch to keep the code bisectable... The patch has been tested on the Marzen board. Signed-off-by:
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Simon Horman authored
This branch acts as a base for adding USB support to r8A7778/BOCK-W and r8A7779/Marzen. It includes the soc branch to provide dependencies in the r8A7778 clock code. It includes pinmux to provide pinmux initialisation for Bock-W which is a dependency. Conflicts: arch/arm/mach-shmobile/Kconfig arch/arm/mach-shmobile/include/mach/r8a7778.h arch/arm/mach-shmobile/setup-r8a7778.c
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- 07 Jun, 2013 24 commits
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Guennadi Liakhovetski authored
According to the datasheet, it is not allowed to change div4 clock rates if an earlier rate change operation is still in progress, as indicated by a set kick bit. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by:
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Guennadi Liakhovetski authored
An earlier commit "ARM: shmobile: sh73a0: add support for adjusting CPU frequency" intended to replace some clock operations only for the Z-clock, instead it replaced them for all div4 clocks, since all div4 clocks share the same copy of clock operations. Fix this by using a separate clock operations structure for Z-clock. Signed-off-by:
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Magnus Damm authored
Break out the function sh73a0_init_delay() that now gets called both for the C version of the code and the DT -reference boards. This way we handle both cases in the same way. Allows us to boot with TWD only in the kernel configuration for C board code. TWD is not yet enabled in the case of DT -reference - this due to a dependency on CCF. Signed-off-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
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Guennadi Liakhovetski authored
This patch enables the use of the generic cpufreq-cpu0 driver on sh73a0. Providing a regulator, a list of OPPs in DT, combined with a virtual cpufreq-cpu0 platform device and a clock, attached to it is everything, the cpufreq-cpu0 driver needs. The first sh73a0 platform, implementing such CPUFreq support is kzm9g-reference. Signed-off-by:
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Guennadi Liakhovetski authored
On SH73A0 the output of PLL0 is supplied to two dividers, feeding clock to the CPU core and SGX. Lower CPU frequencies allow the use of lower supply voltages and thus reduce power consumption. Signed-off-by:
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Laurent Pinchart authored
Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Laurent Pinchart authored
Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as non-static. Compiling support for both SoCs thus result in a symbol redefinition. Fix it by defining the arrays as static. Signed-off-by:
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Kuninori Morimoto authored
DIV6 clocks control SD*/MMC* core clocks. Signed-off-by:
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Kuninori Morimoto authored
DIV4 clocks control SD* core clocks. Signed-off-by:
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Kuninori Morimoto authored
Almost all clock needs main clock which is basis clock on r8a7790. This patch adds it, and, set its parent/ratio via MD pin. It is based on v0.05 datasheet Signed-off-by:
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Kuninori Morimoto authored
This patch adds SDHI register function which needs id number (= 0/1/2) Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
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Kuninori Morimoto authored
R-Car M1 has many clocks, and it is possible to read/use clock ratio of these clocks from FRQMRx. But, these ratio are fixed value and these are decided by MD pin status. This patch reads MD pin status, and used fixed ratio clock for other clocks. It was tesed on bock-w board. Signed-off-by:
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Phil Edworthy authored
Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
DIV6 clocks control each core clocks. Signed-off-by:
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Kuninori Morimoto authored
DIV4 clocks control each core clocks. Signed-off-by:
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Kuninori Morimoto authored
PLL clocks are basis clock for other clock. Signed-off-by:
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Kuninori Morimoto authored
Almost all clock needs main clock which is basis clock on r8a73a4. This patch adds it, and, set parent clock via CKSCR register. Signed-off-by:
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Laurent Pinchart authored
Signed-off-by:
Simon Horman <horms@verge.net.au> Signed-off-by:
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Bastian Hecht authored
Add clock association for i2c0 and i2c1 for the new DT names. Signed-off-by:
Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by:
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Bastian Hecht authored
When we use the ethernet device via DT setup, we need to add it to a lookup list until this is properly handled later in a DT-only fashion. Signed-off-by:
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Kuninori Morimoto authored
Ether setup code position was scattering. This patch fixes it up Signed-off-by:
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Kuninori Morimoto authored
SH_CLK_SET_RATIO() will be trouble without this patch Signed-off-by:
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Kuninori Morimoto authored
Acked-by:
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- 06 Jun, 2013 3 commits
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Simon Horman authored
Convert code to use DEFINE_RES_MEM*() macros. These macros were already used in this file, this change makes their usage consistent throughout the file. Signed-off-by: -
Sergei Shtylyov authored
The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car M1S which is a SH based SoC. Signed-off-by:
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Laurent Pinchart authored
Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as non-static. Compiling support for both SoCs thus result in a symbol redefinition. Fix it by defining the arrays as static. To avoid further similar issues, also define the main_clks as static. Signed-off-by:
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- 05 Jun, 2013 4 commits
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Laurent Pinchart authored
Replace hardcoded pin numbers with the RCAR_GP_PIN macro to make the code match the documentation. Signed-off-by:
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Laurent Pinchart authored
Initialize r8a7790 pinmuxing and register mappings for the two debug serial ports. Signed-off-by:
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Kuninori Morimoto authored
SCIF0 support as 1st step Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Kuninori Morimoto authored
sh73a0 needs "sh_fsi2", not "sh_fsi2.0" Tested-by:
Hiep Cao Minh <cm-hiep@jinso.co.jp> Acked-by:
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