- 14 Dec, 2015 40 commits
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Rashmica Gupta authored
All users of QPACE have upgraded to QPACE2 so remove the Cell QPACE code. Signed-off-by:
Rashmica Gupta <rashmicy@gmail.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Vipin K Parashar authored
Kernel prints respective warnings about various EPOW events for user information/action after parsing EPOW interrupts. At times below EPOW reset event warning is seen to be flooding kernel log over a period of time. May 25 03:46:34 alp kernel: Non critical power or cooling issue cleared May 25 03:46:52 alp kernel: Non critical power or cooling issue cleared May 25 03:53:48 alp kernel: Non critical power or cooling issue cleared May 25 03:55:46 alp kernel: Non critical power or cooling issue cleared May 25 03:56:34 alp kernel: Non critical power or cooling issue cleared May 25 03:59:04 alp kernel: Non critical power or cooling issue cleared May 25 04:02:01 alp kernel: Non critical power or cooling issue cleared These EPOW reset events are spurious in nature and are triggered by firmware without an actual EPOW event being reset. This patch avoids these multiple EPOW reset warnings by using a counter variable. This variable is incremented every time an EPOW event is reported. Upon receiving a EPOW reset event the same variable is checked to filter out spurious events and decremented accordingly. This patch also improves log messages to better describe EPOW event being reported. Merged adjacent log messages into single one to reduce number of lines printed per event. Signed-off-by:
Kamalesh Babulal <kamalesh@linux.vnet.ibm.com> Signed-off-by:
Vipin K Parashar <vipin@linux.vnet.ibm.com> Signed-off-by:
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Michael Neuling authored
Test the kernels signal generation code to ensure it can handle an invalid stack pointer when transactional. Signed-off-by:
Michael Neuling <mikey@neuling.org> Tested-by:
Anshuman Khandual <khandual@linux.vnet.ibm.com> [mpe: Skip if we don't have TM] Signed-off-by:
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Michael Neuling authored
Test the kernel's signal return code to ensure that it doesn't crash when both the transactional and suspend MSR bits are set in the signal context. Signed-off-by:
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Michael Ellerman authored
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Michael Ellerman authored
Move have_htm_nosc() into a new tm.h, and add a new helper, have_htm() which we'll use in the next patch. Signed-off-by: -
Michael Ellerman authored
We already do this twice and want to add another so add a helper. Signed-off-by: -
Michael Ellerman authored
This doesn't really belong in harness.c, it's a helper function. So move it into utils.c. Signed-off-by: -
Michael Ellerman authored
Merge the two TM fixes we merged in 4.4. We are about to merge selftests for these, and without the fixes the selftests will oops. powerpc fixes for 4.4 #2 - tm: Block signal return from setting invalid MSR state from Michael Neuling - tm: Check for already reclaimed tasks from Michael Neuling
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Michael Neuling authored
Print MSR TM bits in oops messages. This appends them to the end like this: MSR: 8000000502823031 <SF,VEC,VSX,FP,ME,IR,DR,LE,TM[TE]> You get the TM[] only if at least one TM MSR bit is set. Inside the TM[], E means Enabled (bit 32), S means Suspended (bit 33), and T means Transactional (bit 34) If no bits are set, you get no TM[] output. Include rework of printbits() to handle this case. Signed-off-by: -
Boqun Feng authored
According to memory-barriers.txt, xchg*, cmpxchg* and their atomic_ versions all need to be fully ordered, however they are now just RELEASE+ACQUIRE, which are not fully ordered. So also replace PPC_RELEASE_BARRIER and PPC_ACQUIRE_BARRIER with PPC_ATOMIC_ENTRY_BARRIER and PPC_ATOMIC_EXIT_BARRIER in __{cmp,}xchg_{u32,u64} respectively to guarantee fully ordered semantics of atomic{,64}_{cmp,}xchg() and {cmp,}xchg(), as a complement of commit b97021f8 ("powerpc: Fix atomic_xxx_return barrier semantics") This patch depends on patch "powerpc: Make value-returning atomics fully ordered" for PPC_ATOMIC_ENTRY_BARRIER definition. Cc: stable@vger.kernel.org # 3.2+ Signed-off-by:Boqun Feng <boqun.feng@gmail.com> Reviewed-by:
Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by:
Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by:
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Boqun Feng authored
According to memory-barriers.txt: > Any atomic operation that modifies some state in memory and returns > information about the state (old or new) implies an SMP-conditional > general memory barrier (smp_mb()) on each side of the actual > operation ... Which mean these operations should be fully ordered. However on PPC, PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation, which is currently "lwsync" if SMP=y. The leading "lwsync" can not guarantee fully ordered atomics, according to Paul Mckenney: https://lkml.org/lkml/2015/10/14/970 To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee the fully-ordered semantics. This also makes futex atomics fully ordered, which can avoid possible memory ordering problems if userspace code relies on futex system call for fully ordered semantics. Fixes: b97021f8 ("powerpc: Fix atomic_xxx_return barrier semantics") Cc: stable@vger.kernel.org # 3.2+ Signed-off-by:
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Aneesh Kumar K.V authored
The slot information of base page size hash pte is stored in the pgtable_t w.r.t transparent hugepage. We need to make sure we don't index beyond pgtable_t size. Signed-off-by:
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by:
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Aneesh Kumar K.V authored
This will bulk read 4 hash pte slot entries and should reduce the loop Signed-off-by:
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Aneesh Kumar K.V authored
Remove the related functions and #defines Signed-off-by:
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Aneesh Kumar K.V authored
They don't need to track 4k subpage slot details and hence don't need second half of pgtable_t. Signed-off-by:
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Aneesh Kumar K.V authored
Use the #define instead of open-coding the same Signed-off-by:
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Aneesh Kumar K.V authored
pte and pmd table size are dependent on config items. Don't hard code the same. This make sure we use the right value when masking pmd entries and also while checking pmd_bad Signed-off-by:
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Aneesh Kumar K.V authored
For a pte entry we will have _PAGE_PTE set. Our pte page address have a minimum alignment requirement of HUGEPD_SHIFT_MASK + 1. We use the lower 7 bits to indicate hugepd. ie. For pmd and pgd we can find: 1) _PAGE_PTE set pte -> indicate PTE 2) bits [2..6] non zero -> indicate hugepd. They also encode the size. We skip bit 1 (_PAGE_PRESENT). 3) othewise pointer to next table. Acked-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Aneesh Kumar K.V authored
We support THP only with book3s_64 and 64K page size. Move THP details to hash64-64k.h to clarify the same. Acked-by:
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Aneesh Kumar K.V authored
W.r.t hugetlb, we support two format for pmd. With book3s_64 and 64K linux page size, we can have pte at the pmd level. Hence we don't need to support hugepd there. For everything else hugepd is supported and pmd_huge is (0). Acked-by:
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Aneesh Kumar K.V authored
Only difference here is, we apply the WIMG mapping early, so rflags passed to updatepp will also be changed. Acked-by:
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Aneesh Kumar K.V authored
Instead of open coding it in multiple code paths, export the helper and add more documentation. Also make sure we don't make assumption regarding pte bit position Acked-by:
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Aneesh Kumar K.V authored
This is similar to 64K insert. May be we want to consolidate Acked-by:
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Aneesh Kumar K.V authored
Convert from asm to C Acked-by:
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Aneesh Kumar K.V authored
No real change, only style changes Acked-by:
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Aneesh Kumar K.V authored
Signed-off-by:
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Aneesh Kumar K.V authored
This free up 11 bits in pte_t. In the later patch we also change the pte_t format so that we can start supporting migration pte at pmd level. We now track 4k subpage valid bit as below If we have _PAGE_COMBO set, we override the _PAGE_F_GIX_SHIFT and _PAGE_F_SECOND. Together we have 4 bits, each of them used to indicate whether any of the 4 4k subpage in that group is valid. ie, [ group 1 bit ] [ group 2 bit ] ..... [ group 4 ] [ subpage 1 - 4] [ subpage 5- 8] ..... [ subpage 13 - 16] We still track each 4k subpage slot number and secondary hash information in the second half of pgtable_t. Removing the subpage tracking have some significant overhead on aim9 and ebizzy benchmark and to support THP with 4K subpage, we do need a pgtable_t of 4096 bytes. Signed-off-by:
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Aneesh Kumar K.V authored
We should not expect pte bit position in asm code. Simply by moving part of that to C Acked-by:
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
Move the booke related headers below booke/32 or booke/64 Acked-by:
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Aneesh Kumar K.V authored
functions which operate on pte bits are moved to hash*.h and other generic functions are moved to pgtable.h Acked-by:
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Aneesh Kumar K.V authored
This enables us to keep hash64 related bits together, and makes it easy to follow. Acked-by:
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Aneesh Kumar K.V authored
We convert them static inline function here as we did with pte_val in the previous patch Acked-by:
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Aneesh Kumar K.V authored
We also convert few #define to static inline in this patch for better type checking Acked-by:
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Aneesh Kumar K.V authored
We copy only needed PTE bits define from pte-common.h to respective hash related header. This should greatly simply later patches in which we are going to change the pte format for hash config Acked-by:
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Aneesh Kumar K.V authored
We are going to drop pte_common.h in the later patch. The idea is to enable hash code not require to define all PTE bits. Having PTE bits defined in pte_common.h made the code unnecessarily complex. Acked-by:
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Aneesh Kumar K.V authored
We also move __ASSEMBLY__ towards the end of header. This avoid having #ifndef __ASSEMBLY___ all over the header Acked-by:
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Aneesh Kumar K.V authored
This further make a copy of pte defines to book3s/64/hash*.h. This remove the dependency on pgtable-ppc64-4k.h and pgtable-ppc64-64k.h Acked-by:
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Aneesh Kumar K.V authored
In this patch we do: cp pgtable-ppc32.h book3s/32/pgtable.h cp pgtable-ppc64.h book3s/64/pgtable.h This enable us to do further changes to hash specific config. We will change the page table format for 64bit hash in later patches. Acked-by:
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