- 06 Oct, 2010 34 commits
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Dave Airlie authored
* 'drm-radeon-next' of ../drm-radeon-next: drm/radeon/kms: add drm blit support for evergreen drm/radeon: Modify radeon_pm_in_vbl to use radeon_get_crtc_scanoutpos() drm/radeon: Add function for display scanout position query. drm/radeon/kms: rework spread spectrum handling drm/radeon/kms: remove new pll algo drm/radeon/kms: remove some pll algo flags drm/radeon/kms: prefer high post dividers in legacy pll algo drm/radeon/kms: properly handle 40 bit MC addresses in the cursor code drm/radeon: add properties to configure the width of the underscan borders drm/radeon/kms/r6xx+: use new style fencing (v3) drm/radeon/kms: enable writeback (v2) drm/radeon/kms: clean up r6xx/r7xx blit init (v2)
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Dave Airlie authored
* drm-kdb-next: drm/nouveau/kms: Avoid a hang entering KDB with VT accel on. radeon, kdb, kms: Save and restore the LUT on atomic KMS enter/exit drm, kdb, kms: Add an enter argument to mode_set_base_atomic() API drm/nouveau/kms: Implement KDB debug hooks for nouveau KMS. drm/radeon/kms: Implement KDB debug hooks for radeon KMS.
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Dave Airlie authored
[airlied - add fix for vmwgfx build] * 'nouveau/for-airlied' of ../drm-nouveau-next: (93 commits) drm/ttm: restructure to allow driver to plug in alternate memory manager drm/ttm: introduce utility function to free an allocated memory node drm/nouveau: fix thinkos in mem timing table recordlen check drm/nouveau: parse voltage from perf 0x40 entires drm/nouveau: don't use the default pll limits in table v2.1 on nv50+ cards drm/nv50: Fix large 3D performance regression caused by the interchannel sync patches. drm/nouveau: Synchronize buffer object moves in hardware. drm/nouveau: Use semaphores to handle inter-channel sync in hardware. drm/nouveau: Provide a means to have arbitrary work run on fence completion. drm/nouveau: Minor refactoring/cleanup of the fence code. drm/nouveau: Add a module option to force card POST. drm/nv50: prevent (IB_PUT == IB_GET) for occurring unless idle drm/nv0x-nv4x: Leave the 0x40 bit untouched when changing CRE_LCD. drm/nv30-nv40: Fix postdivider mask when writing engine/memory PLLs. drm/nouveau: Fix perf table parsing on BMP v5.25. drm/nouveau: fix required mode bandwidth calculation for DP drm/nouveau: fix typo in c2aa91afea5f7e7ae4530fabd37414a79c03328c drm/nva3: split pm backend out from nv50 drm/nouveau: run perflvl and M table scripts on mem clock change drm/nouveau: pass perflvl struct to clock_pre() ...
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Chris Ball authored
Francisco Jerez advises that pre-nv20 cards would hang if we entered kdb with accel on and IRQs disabled, so we now disable accel before entering kdb and re-enable it on the way back out. Reported-by:
Francisco Jerez <currojerez@riseup.net> Signed-off-by:
Chris Ball <cjb@laptop.org> Signed-off-by:
Jason Wessel <jason.wessel@windriver.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Jason Wessel authored
When changing VTs non-atomically the kernel works in conjunction with the Xserver in user space and receives the LUT information from the Xserver via a system call. When changing modes atomically for kdb, this information must be saved and restored without disturbing user space as if nothing ever happened. Signed-off-by:
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Jason Wessel authored
Some devices such as the radeon chips receive information from user space which needs to be saved when executing an atomic mode set operation, else the user space would have to be queried again for the information. This patch extends the mode_set_base_atomic() call to pass an argument to indicate if this is an entry or an exit from an atomic kernel mode set change. Individual drm drivers can properly save and restore state accordingly. Signed-off-by:
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Chris Ball authored
Tested on nv50 and nv04 HW. Signed-off-by:
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Chris Ball authored
Signed-off-by:
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Dave Airlie authored
* drm-vmware-next: drm/vmwgfx: Bump minor and driver date drm/vmwgfx: Save at least one screen layout drm/vmwgfx: Add modinfo version drm/vmwgfx: Add a parameter to get the max fb size drm/vmwgfx: Don't flush fb if we're in the suspended state. drm/vmwgfx: Prune modes based on available VRAM size drm/vmwgfx: Take the ttm lock around the dirty ioctl drm: vmwgfx: Add a struct drm_file parameter to the dirty framebuffer callback drm/vmwgfx: Add new-style PM hooks to improve hibernation behavior drm/vmwgfx: Fix ACPI S3 & S4 functionality. drm/vmwgfx: Really support other depths than 32
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Alex Deucher authored
This patch implements blit support for bo moves using the 3D engine. It uses the same method as r6xx/r7xx: - store the base state in an IB - emit variable state and vertex buffers to do the blit This allows the hw to move bos using the 3D engine and allows full use of vram beyond the pci aperture size. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Mario Kleiner authored
radeon_pm_in_vbl() didn't report in vblank status accurately. Make it a wrapper around radeon_get_crtc_scanoutpos() which corrects for biases, so it reports accurately. radeon_pm_in_vbl() will only report in_vbl if all active crtc's are currently inside vblank. agd5f: use rdev->num_crtc rather than hardcoding the crtc count Signed-off-by:
Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by:
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Mario Kleiner authored
radeon_get_crtc_scanoutpos() returns the current horizontal and vertical scanout position of a crtc. It also reports if the display scanout is currently inside the vblank area. hpos reports current horizontal pixel scanout position. vpos reports the current scanned out line as a value >= 0 in active scanout. If the scanout is inside vblank area, it reports a negative value, the number of scanlines until end of vblank aka start of active scanout, e.g., -3 == "At most 3 scanlines until end of vblank". This code is derived from radeon_pm_in_vbl(), tested on R500 and R600. Signed-off-by:
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Alex Deucher authored
This patch reworks spread spectrum handling to enable it properly on lvds and DP/eDP links. It also fixes several bugs in the old spread spectrum code. - Use the ss recommended reference divider if available when calculating the pll - Use the proper ss command tables on pre-DCE3 asics - Avoid reading past the end of the ss info tables - Enable ss on evergreen asics (lvds, dp, tmds) - Enable ss on DP/eDP links Signed-off-by:
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Alex Deucher authored
The recent changes to the old algo (prefer high post div) coupled with the range and precision limitations of using fixed point with the new algo make the new algo less useful. So drop the new algo. This should work as well or better than the old new/old combinations and simplifies the code a lot. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=30218 among others. Signed-off-by:
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Alex Deucher authored
These shouldn't be needed with the post div changes in the last patch. Signed-off-by:
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Alex Deucher authored
the hw prefers higher post dividers Signed-off-by:
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Alex Deucher authored
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Marius Gröger authored
This allows for a more exact fitting on the physical display. The new properties default to zero which corresponds to the previous underscan border width[height] formula: (display_width[display_width] >> 5) + 16. Example to set a horizontal border width of 30 and a vertikal border height of 22: xrandr --output HDMI-0 --set underscan on --set "underscan hborder" 30 --set "underscan vborder" 22 Signed-off-by:
Marius Gröger <marius.groeger@googlemail.com> Reviewed-by:
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Alex Deucher authored
On r6xx+ a newer fence mechanism was implemented to replace the old wait_until plus scratch regs setup. A single EOP event will flush the destination caches, write a fence value, and generate an interrupt. This is the recommended fence mechanism on r6xx+ asics. This requires my previous writeback patch. v2: fix typo that enabled event fence checking on all asics rather than just r6xx+. v3: properly enable EOP interrupts Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=29972Signed-off-by:
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Alex Deucher authored
When writeback is enabled, the GPU shadows writes to certain registers into a buffer in memory. The driver can then read the values from the shadow rather than reading back from the register across the bus. Writeback can be disabled by setting the no_wb module param to 1. On r6xx/r7xx/evergreen, the following registers are shadowed: - CP scratch registers - CP read pointer - IH write pointer On r1xx-rr5xx, the following registers are shadowed: - CP scratch registers - CP read pointer v2: - Combine wb patches for r6xx-evergreen and r1xx-r5xx - Writeback is disabled on AGP boards since it tends to be unreliable on AGP using the gart. - Check radeon_wb_init return values properly. Signed-off-by:
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Alex Deucher authored
Move common code to init function. v2: make sure the bo is pinned after init as well. Signed-off-by:
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Thomas Hellstrom authored
Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by:
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Thomas Hellstrom authored
Save at least one screen layout during vga save to avoid odd things happening during restore. Signed-off-by:
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Thomas Hellstrom authored
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Thomas Hellstrom authored
This can be used by the X server to restrict mode resolutions and size of root pixmap. Bump minor to announce this availability. Bump driver date. Signed-off-by:
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Thomas Hellstrom authored
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Thomas Hellstrom authored
This needs to be reviewed once we support screen objects and don't rely on VRAM for the frame-buffer. Also fix some integer overflow issues pointed out by Michel Daenzer. Signed-off-by:
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Thomas Hellstrom authored
This makes sure noone accesses the fifo while it's taken down using the dirty ioctl. Also make sure all workqueues are idled before the fifo is taken down. Signed-off-by:
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Thomas Hellstrom authored
This is needed for the callback to identify the caller and take appropriate locks if needed. Signed-off-by:
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Thomas Hellstrom authored
Add the new-style PM hooks prepare and complete. This allows us to power up the device again after the hibernation image has been created, and display output will thus be active until the VM is finally powered off. Signed-off-by:
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Thomas Hellstrom authored
Don't suspend or hibernate when there are 3D resources active since we can't restore the device's 3D state. Instead fail with an error message. In other cases, make sure we re-enable the fifo and unlock ttm on resume. Signed-off-by:
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Thomas Hellstrom authored
Also add some sanity checks. Signed-off-by:
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Dave Airlie authored
necessary for some of the vmware fixes to be pushed in. Conflicts: drivers/gpu/drm/drm_gem.c drivers/gpu/drm/i915/intel_fb.c include/drm/drmP.h
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Dave Airlie authored
* 'intel/drm-intel-next' of ../drm-next: (266 commits) drm/i915: Avoid circular locking from intel_fbdev_fini() drm/i915: mark display port DPMS state as 'ON' when enabling output drm/i915: Skip pread/pwrite if size to copy is 0. drm/i915: avoid struct mutex output_poll mutex lock loop on unload drm/i915: Rephrase pwrite bounds checking to avoid any potential overflow drm/i915: Sanity check pread/pwrite drm/i915: Use pipe state to tell when pipe is off drm/i915: vblank status not valid while training display port drivers/gpu/drm/i915/i915_gem.c: Add missing error handling code drm/i915: Don't mask the return code whilst relocating. drm/i915: If the GPU hangs twice within 5 seconds, declare it wedged. drm/i915: Only print 'generating error event' if we actually are drm/i915: Try to reset gen2 devices. drm/i915: Clear fence registers on GPU reset drm/i915: Force the domain to CPU on unbinding whilst wedged. drm: Move the GTT accounting to i915 drm/i915: Fix refleak during eviction. i915: Added function to initialize VBT settings drm/i915: Remove redundant deletion of obj->gpu_write_list drm/i915: Make get/put pages static ...
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- 05 Oct, 2010 2 commits
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Ben Skeggs authored
Nouveau will need this on GeForce 8 and up to account for the GPU reordering physical VRAM for some memory types. Reviewed-by:
Jerome Glisse <jglisse@redhat.com> Acked-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Existing core code/drivers call drm_mm_put_block on ttm_mem_reg.mm_node directly. Future patches will modify TTM behaviour in such a way that ttm_mem_reg.mm_node doesn't necessarily belong to drm_mm. Reviewed-by:
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- 04 Oct, 2010 4 commits
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Roy Spliet authored
Signed-off-by: -
Ben Skeggs authored
This was disabled previously because of some uncertainty that +2 was indeed the voltage. It appears it is, checked on a NVA8 and a NVA3M. Signed-off-by: -
Emil Velikov authored
This fixes issues bug 30370 and prevents another possible divide by zero on the original nv50 cards, by returning -ENOENT Signed-off-by:
Emil Velikov <eeydev@nottingham.ac.uk> Signed-off-by:
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Francisco Jerez authored
Reported-by:
Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by:
Maarten Maathuis <madman2003@gmail.com> Tested-by:
Xavier Chantry <chantry.xavier@gmail.com> Tested-by:
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