- 20 Aug, 2007 10 commits
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Josh Boyer authored
Add a bootwrapper for the AMCC 440EP Bamboo Eval board. This also adds a common fixup_clock function for all 440EP(x) chips. Signed-off-by:
Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by:
David Gibson <david@gibson.dropbear.id.au>
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Josh Boyer authored
Add support for the AMCC Bamboo board Signed-off-by:
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Josh Boyer authored
AMCC Bamboo board DTS Signed-off-by: -
Josh Boyer authored
Remove inclusion of __res on 40x. We don't need it in arch/powerpc Signed-off-by:
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Josh Boyer authored
Allow generic_calibrate_decr to work for 40x platforms. Given that the hardware behavior is identical, this also changes the set_dec function to reload the PIT on 40x to match the behavior 44x currently has. Signed-off-by: -
Josh Boyer authored
Add MMU definitions for 40x platforms. Also fixes two warnings in 40x_mmu.c. Signed-off-by:
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Josh Boyer authored
Make the fixup_memsize function common for all of 4xx as several chips share the same SDRAM controller. Also add functions to reset 40x chips and quiesce the ethernet. Signed-off-by: -
Josh Boyer authored
Rename the 44x.c wrapper file to 4xx.c. This will allow us to add common functions in a single file that can be shared across all of 4xx. Signed-off-by:
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Josh Boyer authored
Remove some leftover cruft in the 40x Kconfig file. Also make sure we select WANT_DEVICE_TREE for 40x. Signed-off-by:
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Josh Boyer authored
4xx is a bit of a misnomer for certain things, as they really apply to PowerPC 40x only. Rename some of the files to clean this up. Signed-off-by:
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- 17 Aug, 2007 30 commits
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Stephen Rothwell authored
Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Guennadi Liakhovetski authored
Use strlcpy() to guarantee strings in i2c device type and driver_name fields are 0-terminated. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
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Stephen Rothwell authored
These functions are only called by __init functions. WARNING: vmlinux.o(.text+0x56aa0): Section mismatch: reference to .init.text:.lmb_alloc (between '.iob_init' and '.iommu_init_early_pasemi') Signed-off-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
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Stephen Rothwell authored
The functions are only called from __init functions. WARNING: vmlinux.o(.text+0x45ed0): Section mismatch: reference to .init.text:.btext_find_display (between '.udbg_adb_init_early' and '.udbg_adb_init') WARNING: vmlinux.o(.text+0x45f9c): Section mismatch: reference to .init.text:.btext_find_display (between '.udbg_adb_init' and '.udbg_adb_getc_poll') WARNING: vmlinux.o(.text+0x46000): Section mismatch: reference to .init.text:.find_via_pmu (between '.udbg_adb_init' and '.udbg_adb_getc_poll') Signed-off-by:
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Stephen Rothwell authored
These functions are only called from __init functions. WARNING: vmlinux.o(.text+0x398f4): Section mismatch: reference to .init.text:.lmb_alloc (between '.iommu_init_early_dart' and '.pci_dma_bus_setup_dart') Signed-off-by:
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Stephen Rothwell authored
WARNING: vmlinux.o(.text+0x23258): Section mismatch: reference to .init.text:.lmb_reserve (between '.reserve_kdump_trampoline' and '.restore_processor_state') Signed-off-by:
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David Gibson authored
At present the cascade interrupt handler for the UIC (interrupt controller on 4xx embedded chips) will misbehave badly if it is called spuriously - that is if the handler is invoked when no interrupts are asserted in the child UIC. Although spurious interrupts shouldn't happen, it's good to behave robustly if they do. This patch does so by checking for and ignoring spurious interrupts. Signed-off-by:
Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by:
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David Gibson authored
At present the driver for the UIC (the embedded interrupt controller in 4xx chips) uses the handle_level_irq() flow handler. It turns out this does not correctly handle level triggered interrupts on the UIC. Specifically, acknowledging an irq on the UIC (i.e. clearing the relevant bit in UIC_SR) will have no effect for a level interrupt which is still asserted by the external device, even if the irq is already masked. Therefore, unlike handle_level_irq() we must ack the interrupt after invoking the ISR (which should cause the device to stop asserting the irq) instead of acking it when we mask it, before the ISR. This patch implements this change, in a new handle_uic_irq(), a customised irq flow handler for the UIC. For edge triggered interrupts, handle_uic_irq() still uses the old flow - we must ack edge triggered interrupt before the ISR not after, or we could miss a second event which occurred between invoking the ISR and acking the irq. Signed-off-by:
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David Gibson authored
The UIC (interrupt controller in 4xx embedded CPUs) driver currently missets the IRQ_lEVEL flag in desc->status, due to a thinko. This patch fixes the bug. Currently this is only a cosmetic problem (affects the output in /proc/interrupts), however subsequent patches will use the IRQ_LEVEL flag to affect flow handling. Signed-off-by:
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Stephen Rothwell authored
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Stephen Rothwell authored
This removes some of the #ifdefs from .c files. Signed-off-by:
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Stephen Rothwell authored
They were only needed for backwards compatibility and all in tree uses have now been changed. Signed-off-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
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Stephen Rothwell authored
get_property has been renamed to of_get_property. Signed-off-by:
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Stephen Rothwell authored
arch/powerpc/mm/mmu_context_64.c: In function 'init_new_context': arch/powerpc/mm/mmu_context_64.c:31: warning: unused variable 'new_context' Signed-off-by:
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Becky Bruce authored
This file was protected by _PPC64_LMB_H, which is confusing, as the 32-bit code also uses the lmb these days. Changed to _ASM_POWERPC_LMB_H. Signed-off-by:
Becky Bruce <becky.bruce@freescale.com> Signed-off-by:
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Michael Buesch authored
This fixes a typo in a printk message. Signed-off-by:
Michael Buesch <mb@bu3sch.de> Acked-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Segher Boessenkool authored
Instead, use asm() like all other atomic operations already do. Also use inline functions instead of macros; this actually improves code generation (some code becomes a little smaller, probably because of improved alias information -- just a few hundred bytes total on a default kernel build, nothing shocking). Signed-off-by:
Segher Boessenkool <segher@kernel.crashing.org> Signed-off-by:
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Paul Mackerras authored
This adds code to handle alignment traps generated by the following new floating-point load/store instructions, by emulating the instruction in the kernel (as is done for other instructions that generate alignment traps): lfiwax load floating-point as integer word algebraic indexed stfiwx store floating-point as integer word indexed lfdp load floating-point double pair lfdpx load floating-point double pair indexed stfdp store floating-point double pair stfdpx store floating-point double pair indexed All these except stfiwx are new in POWER6. lfdp/lfdpx/stfdp/stfdpx load and store 16 bytes of memory into an even/odd FP register pair. In little-endian mode each 8-byte value is byte-reversed separately (i.e. not as a 16-byte unit). lfiwax/stfiwx load or store the lower 4 bytes of a floating-point register from/to memory; lfiwax sets the upper 4 bytes of the FP register to the sign extension of the value loaded. Signed-off-by: -
Linas Vepstas authored
Remove dead code, and a misleading comment about EEH checking for video devices. The removed code is a left-over from the olden days where there was concern over how video devices worked in Linux. We are never going to go that way again, so kill this. Signed-off-by:
Linas Vepstas <linas@austin.ibm.com> ---- arch/powerpc/platforms/pseries/eeh.c | 17 ----------------- 1 file changed, 17 deletions(-) Signed-off-by:
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Nathan Lynch authored
The powermac pci configuration space write methods read the written location immediately after the write is performed, presumably in order to flush the write. However, configuration space writes are not allowed to be posted, making these reads gratuitous. Furthermore, this behavior potentially causes us to violate the PCI PM spec when changing between e.g. D0 and D3 states, because a delay of up to 10ms may be required before the OS accesses configuration space after the write which initiates the transition. Remove the unnecessary reads from macrisc_write_config, u3_ht_write_config, and u4_pcie_write_config. Signed-off-by:
Nathan Lynch <ntl@pobox.com> Signed-off-by:
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Nathan Lynch authored
The pasemi pci configuration space write method reads the written location immediately after the write is performed, presumably in order to flush the write. However, configuration space writes are not allowed to be posted, making these reads gratuitous. Furthermore, this behavior potentially causes us to violate the PCI PM spec when changing between e.g. D0 and D3 states, because a delay of up to 10ms may be required before the OS accesses configuration space after the write which initiates the transition. Remove the unnecessary reads from pa_pxp_write_config. Signed-off-by:
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Nathan Lynch authored
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Nathan Lynch authored
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Nathan Lynch authored
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Nathan Lynch authored
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Nathan Lynch authored
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Nathan Lynch authored
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Nathan Lynch authored
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Nathan Lynch authored
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Nathan Lynch authored
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